pan/bi: Restrict registers to r0-r15 when compiling blend shaders
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8417>
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@ -74,8 +74,8 @@ bi_allocate_registers(bi_context *ctx, bool *success)
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if (ctx->is_blend) {
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/* R0-R3 are reserved for the blend input */
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l->class_start[BI_REG_CLASS_WORK] = 4 * 4;
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l->class_size[BI_REG_CLASS_WORK] = 64 * 4;
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l->class_start[BI_REG_CLASS_WORK] = 0;
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l->class_size[BI_REG_CLASS_WORK] = 16 * 4;
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} else {
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/* R0 - R63, all 32-bit */
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l->class_start[BI_REG_CLASS_WORK] = 0;
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