From f61be082d32e0ada4e4ac9b8d81ec84fd32726ad Mon Sep 17 00:00:00 2001
From: Boris Brezillon <boris.brezillon@collabora.com>
Date: Fri, 8 Jan 2021 19:18:36 +0100
Subject: [PATCH] pan/bi: Restrict registers to r0-r15 when compiling blend
 shaders

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8417>
---
 src/panfrost/bifrost/bi_ra.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/panfrost/bifrost/bi_ra.c b/src/panfrost/bifrost/bi_ra.c
index c3c216bf251..0be5bdbf62f 100644
--- a/src/panfrost/bifrost/bi_ra.c
+++ b/src/panfrost/bifrost/bi_ra.c
@@ -74,8 +74,8 @@ bi_allocate_registers(bi_context *ctx, bool *success)
 
         if (ctx->is_blend) {
                 /* R0-R3 are reserved for the blend input */
-                l->class_start[BI_REG_CLASS_WORK] = 4 * 4;
-                l->class_size[BI_REG_CLASS_WORK] = 64 * 4;
+                l->class_start[BI_REG_CLASS_WORK] = 0;
+                l->class_size[BI_REG_CLASS_WORK] = 16 * 4;
         } else {
                 /* R0 - R63, all 32-bit */
                 l->class_start[BI_REG_CLASS_WORK] = 0;