diff --git a/src/amd/compiler/aco_shader_info.h b/src/amd/compiler/aco_shader_info.h
index 07b372da27a..92eab124b4c 100644
--- a/src/amd/compiler/aco_shader_info.h
+++ b/src/amd/compiler/aco_shader_info.h
@@ -126,6 +126,7 @@ struct aco_shader_info {
       bool writes_z;
       bool writes_stencil;
       bool writes_sample_mask;
+      bool has_epilog;
       uint32_t num_interp;
       unsigned spi_ps_input;
    } ps;
diff --git a/src/amd/vulkan/radv_aco_shader_info.h b/src/amd/vulkan/radv_aco_shader_info.h
index a138380b152..0f6b64a2b8d 100644
--- a/src/amd/vulkan/radv_aco_shader_info.h
+++ b/src/amd/vulkan/radv_aco_shader_info.h
@@ -95,6 +95,7 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info,
    ASSIGN_FIELD(ps.writes_z);
    ASSIGN_FIELD(ps.writes_stencil);
    ASSIGN_FIELD(ps.writes_sample_mask);
+   ASSIGN_FIELD(ps.has_epilog);
    ASSIGN_FIELD(ps.num_interp);
    ASSIGN_FIELD(ps.spi_ps_input);
    ASSIGN_FIELD(cs.subgroup_size);
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index d6a24f5a992..2fe53407d2f 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3374,6 +3374,8 @@ radv_generate_graphics_pipeline_key(const struct radv_graphics_pipeline *pipelin
    if (device->primitives_generated_query)
       key.primitives_generated_query = true;
 
+   key.ps.has_epilog = false; /* TODO: hook up PS epilogs */
+
    return key;
 }
 
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index bcca4aa430b..e8a693129bc 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -104,6 +104,8 @@ struct radv_pipeline_key {
 
       /* Used to export alpha through MRTZ for alpha-to-coverage (GFX11+). */
       bool alpha_to_coverage_via_mrtz;
+
+      bool has_epilog;
    } ps;
 
    struct {
@@ -337,6 +339,7 @@ struct radv_shader_info {
       uint8_t reads_sample_pos_mask;
       uint8_t depth_layout;
       bool allow_flat_shading;
+      bool has_epilog;
       unsigned spi_ps_input;
    } ps;
    struct {
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index 61317c88cbd..0c8e933cd22 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -479,6 +479,12 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n
       info->vs.use_per_attribute_vb_descs = device->robust_buffer_access || info->vs.dynamic_inputs;
    }
 
+   if (nir->info.stage == MESA_SHADER_FRAGMENT) {
+      if (pipeline_key->ps.has_epilog) {
+         info->ps.has_epilog = true;
+      }
+   }
+
    /* We have to ensure consistent input register assignments between the main shader and the
     * prolog. */
    info->vs.needs_instance_id |= info->vs.has_prolog;