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ac/surface: enable DCC image stores for all displayable DCC on gfx10.3 

Co-authored-by: Joshua Ashton <joshua@froggi.es>
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13153>
This commit is contained in:
Marek Olšák 2021-10-01 22:59:18 +01:00 committed by Marge Bot
parent e76956b9e0
commit edc8a4a037
1 changed files with 29 additions and 8 deletions
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37
src/amd/common/ac_surface.c
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@ -107,10 +107,17 @@ bool ac_modifier_has_dcc_retile(uint64_t modifier)
bool ac_modifier_supports_dcc_image_stores(uint64_t modifier)
{
return ac_modifier_has_dcc(modifier) &&
!AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier) &&
AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier) &&
AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier) == AMD_FMT_MOD_DCC_BLOCK_128B;
if (!ac_modifier_has_dcc(modifier))
return false;
return (!AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier) &&
AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier) &&
AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier) == AMD_FMT_MOD_DCC_BLOCK_128B) ||
(AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && /* gfx10.3 */
AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier) &&
AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier) &&
AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier) == AMD_FMT_MOD_DCC_BLOCK_64B);
}
@ -121,18 +128,32 @@ bool ac_surface_supports_dcc_image_stores(enum chip_class chip_class,
if (chip_class < GFX10)
return false;
/* DCC image stores require the following settings:
/* DCC image stores support the following settings:
* - INDEPENDENT_64B_BLOCKS = 0
* - INDEPENDENT_128B_BLOCKS = 1
* - MAX_COMPRESSED_BLOCK_SIZE = 128B
* - MAX_UNCOMPRESSED_BLOCK_SIZE = 256B (always used)
*
* gfx10.3 also supports the following setting:
* - INDEPENDENT_64B_BLOCKS = 1
* - INDEPENDENT_128B_BLOCKS = 1
* - MAX_COMPRESSED_BLOCK_SIZE = 64B
* - MAX_UNCOMPRESSED_BLOCK_SIZE = 256B (always used)
*
* The compressor only looks at MAX_COMPRESSED_BLOCK_SIZE to determine
* the INDEPENDENT_xx_BLOCKS settings. 128B implies INDEP_128B, while 64B
* implies INDEP_64B && INDEP_128B.
*
* The same limitations apply to SDMA compressed stores because
* SDMA uses the same DCC codec.
*/
return !surf->u.gfx9.color.dcc.independent_64B_blocks &&
surf->u.gfx9.color.dcc.independent_128B_blocks &&
surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B;
return (!surf->u.gfx9.color.dcc.independent_64B_blocks &&
surf->u.gfx9.color.dcc.independent_128B_blocks &&
surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B) ||
(chip_class >= GFX10_3 && /* gfx10.3 */
surf->u.gfx9.color.dcc.independent_64B_blocks &&
surf->u.gfx9.color.dcc.independent_128B_blocks &&
surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
}
static