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pan/midgard: Report spills:fills to shader-db 

Route this info through so we can track how we're doing on register
spilling.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
This commit is contained in:
Alyssa Rosenzweig 2019-07-22 06:32:48 -07:00
parent 055aa9b1f4
commit e8dca7e1e1
3 changed files with 12 additions and 2 deletions
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4
src/panfrost/midgard/compiler.h
View File

@ -197,6 +197,10 @@ typedef struct compiler_context {
/* Number of bytes used for Thread Local Storage */
unsigned tls_size;
/* Count of spills and fills for shaderdb */
unsigned spills;
unsigned fills;
/* Current NIR function */
nir_function *func;

6
src/panfrost/midgard/midgard_compile.c
View File

@ -2741,12 +2741,14 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl
fprintf(stderr, "shader%d - %s shader: "
"%u inst, %u bundles, %u quadwords, "
"%u registers, %u threads, %u loops\n",
"%u registers, %u threads, %u loops, "
"%d:%d spills:fills\n",
SHADER_DB_COUNT++,
gl_shader_stage_name(ctx->stage),
nr_ins, nr_bundles, nr_quadwords,
nr_registers, nr_threads,
ctx->loop_count);
ctx->loop_count,
ctx->spills, ctx->fills);
}

4
src/panfrost/midgard/midgard_schedule.c
View File

@ -720,6 +720,8 @@ schedule_program(compiler_context *ctx)
midgard_instruction st = v_load_store_scratch(ins->ssa_args.dest, spill_slot, true, ins->mask);
mir_insert_instruction_before(mir_next_op(ins), st);
ctx->spills++;
}
/* Insert a load from TLS before the first consecutive
@ -759,6 +761,8 @@ schedule_program(compiler_context *ctx)
/* Rewrite to use */
mir_rewrite_index_src_single(ins, spill_node, consecutive_index);
ctx->fills++;
}
}
}