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panfrost/midgard: Reenable pipeline register creation 

This was disabled to permit regression-free RA work. Now that the spill
code is in place, we can reenable, with some caveats about efficacy.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
This commit is contained in:
Alyssa Rosenzweig 2019-07-19 16:27:39 -07:00
parent f0d0061b18
commit 055aa9b1f4
1 changed files with 9 additions and 10 deletions
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19
src/panfrost/midgard/midgard_schedule.c
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@ -769,19 +769,18 @@ schedule_program(compiler_context *ctx)
g = allocate_registers(ctx, &spilled);
} while(spilled && ((iter_count--) > 0));
/* We would like to run RA after scheduling, but spilling can
* complicate this */
/* After RA finishes, we schedule all at once */
mir_foreach_block(ctx, block) {
schedule_block(ctx, block);
}
#if 0
/* Pipeline registers creation is a prepass before RA */
mir_create_pipeline_registers(ctx);
#endif
mir_foreach_block(ctx, block) {
schedule_block(ctx, block);
}
/* Finally, we create pipeline registers as a peephole pass after
* scheduling. This isn't totally optimal, since there are cases where
* the usage of pipeline registers can eliminate spills, but it does
* save some power */
mir_create_pipeline_registers(ctx);
if (iter_count <= 0) {
fprintf(stderr, "panfrost: Gave up allocating registers, rendering will be incomplete\n");