vc4: Add some spec citations about texture fifo management.
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@ -297,16 +297,48 @@ calculate_forward_deps(struct vc4_compile *c, void *mem_ctx,
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case QOP_TEX_R:
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case QOP_TEX_B:
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case QOP_TEX_DIRECT:
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/* If the texture coordinate fifo is full,
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* block this on the last QOP_TEX_RESULT.
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/* From the VC4 spec:
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*
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* "The TFREQ input FIFO holds two full lots of s,
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* t, r, b data, plus associated setup data, per
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* QPU, that is, there are eight data slots. For
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* each texture request, slots are only consumed
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* for the components of s, t, r, and b actually
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* written. Thus the FIFO can hold four requests
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* of just (s, t) data, or eight requests of just
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* s data (for direct addressed data lookups).
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*
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* Note that there is one FIFO per QPU, and the
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* FIFO has no concept of threads - that is,
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* multi-threaded shaders must be careful to use
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* only 1/2 the FIFO depth before reading
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* back. Multi-threaded programs must also
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* therefore always thread switch on texture
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* fetch as the other thread may have data
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* waiting in the FIFO."
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*
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* If the texture coordinate fifo is full, block this
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* on the last QOP_TEX_RESULT.
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*/
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if (state.tfreq_count == 8) {
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block_until_tex_result(&state, n);
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}
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/* If the texture result fifo is full, block
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* adding any more to it until the last
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* QOP_TEX_RESULT.
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/* From the VC4 spec:
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*
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* "Since the maximum number of texture requests
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* in the input (TFREQ) FIFO is four lots of (s,
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* t) data, the output (TFRCV) FIFO is sized to
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* holds four lots of max-size color data per
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* QPU. For non-float color, reads are packed
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* RGBA8888 data (one read per pixel). For 16-bit
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* float color, two reads are necessary per
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* pixel, with reads packed as RG1616 then
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* BA1616. So per QPU there are eight color slots
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* in the TFRCV FIFO."
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*
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* If the texture result fifo is full, block adding
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* any more to it until the last QOP_TEX_RESULT.
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*/
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if (inst->op == QOP_TEX_S ||
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inst->op == QOP_TEX_DIRECT) {
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