diff --git a/src/panfrost/bifrost/valhall/ISA.xml b/src/panfrost/bifrost/valhall/ISA.xml
index 73eac8b7a84..cc5a1c0bab2 100644
--- a/src/panfrost/bifrost/valhall/ISA.xml
+++ b/src/panfrost/bifrost/valhall/ISA.xml
@@ -477,10 +477,10 @@
f32
f16
+ s32
+ s16
u32
-
-
-
+ u16
@@ -719,12 +719,35 @@
-
+
+
+ Load the effective address of a texel from the image specified with the
+ given immediate index. Returns three staging register: the low/high
+ 32-bits of the address and the internal conversion descriptor. The format
+ of the internal conversion descriptor is compatible with Bifrost but
+ omits the register format, as this is specified with the ST_CVT
+ instruction on Valhall.
+
+ Coordinates are specified as 16-bit integers, packed into 32-bit sources.
+
+
+
+
+
+
+ X/Y coordinates (16:16)
+ Z/W coordinates (16:16)
+
+
+
+
+
+
The index must not diverge within a warp.
+
-
Vertex ID
Instance ID
@@ -856,12 +879,26 @@
-
- Stores to images
+
+
+ Store to memory with data conversion. The address to store to is given in
+ the first source, which must be a 64-bit register (a pair of 32-bit
+ registers). For backwards compatibility with Bifrost, there is a second
+ source which should be the high 32-bits of the register. However, on
+ Valhall the first source is 64-bit so the second source is unused. The
+ third source is the conversion descriptor used for the store.
+
+ Used with LEA_IMAGE_IMM to implement image stores.
+
+
+
- Address to store to after adding offset
+ 64-bit address to store to (low)
+ 64-bit address to store to (high)
+ Internal conversion descriptor
+
diff --git a/src/panfrost/bifrost/valhall/test/assembler-cases.txt b/src/panfrost/bifrost/valhall/test/assembler-cases.txt
index 3361f5a7e0e..ea9f16bfe28 100644
--- a/src/panfrost/bifrost/valhall/test/assembler-cases.txt
+++ b/src/panfrost/bifrost/valhall/test/assembler-cases.txt
@@ -106,3 +106,9 @@ c0 01 00 00 00 c4 10 51 IADD_IMM.i32.reconverge r4, 0x0, #0x1
04 00 00 00 00 c7 91 08 MOV.i32.wait0 r7, r4
42 00 00 38 08 44 61 00 STORE.i128.slot0 @r4:r5:r6:r7, `r2, offset:0
41 f8 ff ff 07 c0 1f 50 BRANCHZ.reconverge `r1, offset:-8
+7d c0 00 08 10 bc a1 00 IADD.v2u16 r60.h1, `r61.h10, 0x0
+44 00 46 32 28 40 71 78 ST_CVT.v4.f32.slot0.return @r0:r1:r2:r3, `r4, r0, `r6, unk:0x2
+44 00 46 34 28 40 71 78 ST_CVT.v4.s32.slot0.return @r0:r1:r2:r3, `r4, r0, `r6, unk:0x2
+44 00 46 36 28 40 71 78 ST_CVT.v4.u32.slot0.return @r0:r1:r2:r3, `r4, r0, `r6, unk:0x2
+7c c0 12 00 26 84 67 00 LEA_IMAGE_IMM.slot0 @r4:r5:r6, `r60, 0x0, unk:0x2, index:0x1, unk2:0x2
+7c c0 02 00 26 84 67 00 LEA_IMAGE_IMM.slot0 @r4:r5:r6, `r60, 0x0, unk:0x2, index:0x0, unk2:0x2