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radv: use correct register setter for ngg hw addr 

this shouldn't matter, but it's good to be correct.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
This commit is contained in:
Dave Airlie 2019-07-17 14:55:52 +10:00
parent 9689407c54
commit de524b2c37
1 changed files with 1 additions and 1 deletions
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2
src/amd/vulkan/radv_pipeline.c
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@ -3428,7 +3428,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
radeon_emit(cs, va >> 8);
radeon_emit(cs, va >> 40);
radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
radeon_emit(cs, shader->config.rsrc1);
radeon_emit(cs, shader->config.rsrc2);