From de524b2c37870d52a5bd31c72ff320f9bf7166f6 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 17 Jul 2019 14:55:52 +1000 Subject: [PATCH] radv: use correct register setter for ngg hw addr this shouldn't matter, but it's good to be correct. Reviewed-by: Samuel Pitoiset --- src/amd/vulkan/radv_pipeline.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index b1b90c8b035..47f3f7887d1 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3428,7 +3428,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2); radeon_emit(cs, va >> 8); - radeon_emit(cs, va >> 40); + radeon_emit(cs, S_00B324_MEM_BASE(va >> 40)); radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2); radeon_emit(cs, shader->config.rsrc1); radeon_emit(cs, shader->config.rsrc2);