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intel/isl: Select Y-tiling for stencil on gen12 

Rework:
 * Disallow linear 1D stencil buffers (Nanley)
 * Force Y for gen12 stencil rather than ~W (Nanley)

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
This commit is contained in:
Jason Ekstrand 2018-01-08 16:28:46 -08:00 committed by Jordan Justen
parent 9dd9c3363b
commit d9565160b2
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GPG Key ID: 37F99F68CAF992EB
1 changed files with 7 additions and 4 deletions
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11
src/intel/isl/isl_gen7.c
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@ -213,11 +213,14 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
*flags &= ISL_TILING_ANY_Y_MASK;
}
/* Separate stencil requires W tiling, and W tiling requires separate
* stencil.
*/
if (isl_surf_usage_is_stencil(info->usage)) {
*flags &= ISL_TILING_W_BIT;
if (ISL_DEV_GEN(dev) >= 12) {
/* Stencil requires Y. */
*flags &= ISL_TILING_ANY_Y_MASK;
} else {
/* Stencil requires W. */
*flags &= ISL_TILING_W_BIT;
}
} else {
*flags &= ~ISL_TILING_W_BIT;
}