From d9565160b289b8ebf3d953e57e156382bc62ecc3 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Mon, 8 Jan 2018 16:28:46 -0800 Subject: [PATCH] intel/isl: Select Y-tiling for stencil on gen12 Rework: * Disallow linear 1D stencil buffers (Nanley) * Force Y for gen12 stencil rather than ~W (Nanley) Co-authored-by: Nanley Chery Reviewed-by: Jason Ekstrand Reviewed-by: Nanley Chery --- src/intel/isl/isl_gen7.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c index a9db21fba52..e1feae9b375 100644 --- a/src/intel/isl/isl_gen7.c +++ b/src/intel/isl/isl_gen7.c @@ -213,11 +213,14 @@ isl_gen6_filter_tiling(const struct isl_device *dev, *flags &= ISL_TILING_ANY_Y_MASK; } - /* Separate stencil requires W tiling, and W tiling requires separate - * stencil. - */ if (isl_surf_usage_is_stencil(info->usage)) { - *flags &= ISL_TILING_W_BIT; + if (ISL_DEV_GEN(dev) >= 12) { + /* Stencil requires Y. */ + *flags &= ISL_TILING_ANY_Y_MASK; + } else { + /* Stencil requires W. */ + *flags &= ISL_TILING_W_BIT; + } } else { *flags &= ~ISL_TILING_W_BIT; }