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i965: Update assertion to account for Gen < 7 

Previously SHADER_OPCODE_MULH could only exist on Gen7+, so the
assertion assumed the Gen7+ accumulator rules.  A future patch will
allow this instruction on at least Gen6, so update the assertion.

v2: Use get_lowered_simd_width instead of open coding it.  Suggested by
Curro.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
This commit is contained in:
Ian Romanick 2016-06-28 14:48:22 -07:00
parent 3e7cebc8da
commit d7a47a76e0
1 changed files with 4 additions and 1 deletions
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5
src/mesa/drivers/dri/i965/brw_fs.cpp
View File

@ -43,6 +43,9 @@
using namespace brw;
static unsigned get_lowered_simd_width(const struct brw_device_info *devinfo,
const fs_inst *inst);
void
fs_inst::init(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
const fs_reg *src, unsigned sources)
@ -3640,7 +3643,7 @@ fs_visitor::lower_integer_multiplication()
} else if (inst->opcode == SHADER_OPCODE_MULH) {
/* Should have been lowered to 8-wide. */
assert(inst->exec_size <= 8);
assert(inst->exec_size <= get_lowered_simd_width(devinfo, inst));
const fs_reg acc = retype(brw_acc_reg(inst->exec_size),
inst->dst.type);
fs_inst *mul = ibld.MUL(acc, inst->src[0], inst->src[1]);