nv50: enable texture query lod
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
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4dc13e3c71
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@ -117,6 +117,7 @@ enum operation
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OP_TXQ, // texture size query
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OP_TXD, // texture derivatives
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OP_TXG, // texture gather
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OP_TXLQ, // texture query lod
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OP_TEXCSAA, // texture op for coverage sampling
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OP_TEXPREP, // turn cube map array into 2d array coordinates
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OP_SULDB, // surface load (raw)
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@ -1450,6 +1450,9 @@ CodeEmitterNV50::emitTEX(const TexInstruction *i)
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code[0] |= 0x01000000;
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code[1] = 0x80000000;
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break;
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case OP_TXLQ:
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code[1] = 0x60020000;
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break;
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default:
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assert(i->op == OP_TEX);
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break;
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@ -1791,6 +1794,7 @@ CodeEmitterNV50::emitInstruction(Instruction *insn)
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case OP_TXL:
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case OP_TXF:
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case OP_TXG:
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case OP_TXLQ:
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emitTEX(insn->asTex());
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break;
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case OP_TXQ:
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@ -255,6 +255,7 @@ unsigned int Instruction::srcMask(unsigned int s) const
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case TGSI_OPCODE_TXD:
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case TGSI_OPCODE_TXL:
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case TGSI_OPCODE_TXP:
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case TGSI_OPCODE_LODQ:
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{
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const struct tgsi_instruction_texture *tex = &insn->Texture;
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@ -559,6 +560,7 @@ static nv50_ir::operation translateOpcode(uint opcode)
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NV50_IR_OPCODE_CASE(TXF, TXF);
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NV50_IR_OPCODE_CASE(TXQ, TXQ);
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NV50_IR_OPCODE_CASE(TG4, TXG);
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NV50_IR_OPCODE_CASE(LODQ, TXLQ);
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NV50_IR_OPCODE_CASE(EMIT, EMIT);
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NV50_IR_OPCODE_CASE(ENDPRIM, RESTART);
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@ -2429,6 +2431,7 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
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case TGSI_OPCODE_TXB:
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case TGSI_OPCODE_TXL:
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case TGSI_OPCODE_TXP:
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case TGSI_OPCODE_LODQ:
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// R S L C Dx Dy
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handleTEX(dst0, 1, 1, 0x03, 0x0f, 0x00, 0x00);
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break;
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@ -543,6 +543,7 @@ private:
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bool handleTXB(TexInstruction *); // I really
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bool handleTXL(TexInstruction *); // hate
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bool handleTXD(TexInstruction *); // these 3
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bool handleTXLQ(TexInstruction *);
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bool handleCALL(Instruction *);
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bool handlePRECONT(Instruction *);
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@ -856,6 +857,26 @@ NV50LoweringPreSSA::handleTXD(TexInstruction *i)
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return true;
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}
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bool
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NV50LoweringPreSSA::handleTXLQ(TexInstruction *i)
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{
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handleTEX(i);
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bld.setPosition(i, true);
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/* The returned values are not quite what we want:
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* (a) convert from s32 to f32
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* (b) multiply by 1/256
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*/
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for (int def = 0; def < 2; ++def) {
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if (!i->defExists(def))
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continue;
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bld.mkCvt(OP_CVT, TYPE_F32, i->getDef(def), TYPE_S32, i->getDef(def));
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bld.mkOp2(OP_MUL, TYPE_F32, i->getDef(def),
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i->getDef(def), bld.loadImm(NULL, 1.0f / 256));
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}
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return true;
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}
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bool
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NV50LoweringPreSSA::handleSET(Instruction *i)
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{
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@ -1197,6 +1218,8 @@ NV50LoweringPreSSA::visit(Instruction *i)
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return handleTXL(i->asTex());
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case OP_TXD:
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return handleTXD(i->asTex());
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case OP_TXLQ:
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return handleTXLQ(i->asTex());
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case OP_EX2:
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bld.mkOp1(OP_PREEX2, TYPE_F32, i->getDef(0), i->getSrc(0));
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i->setSrc(0, i->getDef(0));
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@ -147,6 +147,7 @@ const char *operationStr[OP_LAST + 1] =
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"texquery",
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"texgrad",
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"texgather",
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"texquerylod",
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"texcsaa",
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"texprep",
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"suldb",
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@ -196,12 +196,13 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_TEXTURE_GATHER_SM5:
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case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
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case PIPE_CAP_FAKE_SW_MSAA:
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case PIPE_CAP_TEXTURE_QUERY_LOD:
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return 0;
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case PIPE_CAP_MAX_VIEWPORTS:
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return NV50_MAX_VIEWPORTS;
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case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
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return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
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case PIPE_CAP_TEXTURE_QUERY_LOD:
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return class_3d >= NVA3_3D_CLASS;
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default:
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NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
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return 0;
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