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gallium/radeon: decrease the size of radeon_surf 

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-10-23 15:51:46 +02:00
parent e9590d9092
commit d5c7ea3b83
3 changed files with 36 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/gallium/drivers/radeon/r600_texture.c
View File

@ -929,7 +929,7 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
rtex->surface.bpe, rtex->resource.b.b.nr_samples,
rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
fprintf(f, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
"bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
@ -959,7 +959,7 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
rtex->tc_compatible_htile);
if (rtex->dcc_offset) {
fprintf(f, " DCC: offset=%"PRIu64", size=%"PRIu64", alignment=%"PRIu64"\n",
fprintf(f, " DCC: offset=%"PRIu64", size=%"PRIu64", alignment=%u\n",
rtex->dcc_offset, rtex->surface.dcc_size,
rtex->surface.dcc_alignment);
for (i = 0; i <= rtex->resource.b.b.last_level; i++)

62
src/gallium/drivers/radeon/radeon_winsys.h
View File

@ -255,7 +255,7 @@ enum radeon_feature_id {
RADEON_FID_R300_CMASK_ACCESS,
};
#define RADEON_SURF_MAX_LEVEL 32
#define RADEON_SURF_MAX_LEVELS 15
enum radeon_surf_mode {
RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
@ -278,24 +278,24 @@ enum radeon_surf_mode {
struct radeon_surf_level {
uint64_t offset;
uint64_t slice_size;
uint32_t npix_x;
uint32_t npix_y;
uint32_t npix_z;
uint32_t nblk_x;
uint32_t nblk_y;
uint32_t nblk_z;
uint32_t pitch_bytes;
enum radeon_surf_mode mode;
uint64_t dcc_offset;
uint64_t dcc_fast_clear_size;
uint16_t npix_x;
uint16_t npix_y;
uint16_t npix_z;
uint16_t nblk_x;
uint16_t nblk_y;
uint16_t nblk_z;
uint32_t pitch_bytes;
enum radeon_surf_mode mode;
bool dcc_enabled;
};
struct radeon_surf {
/* Format properties. */
uint32_t blk_w;
uint32_t blk_h;
uint32_t bpe;
unsigned blk_w:4;
unsigned blk_h:4;
unsigned bpe:5;
uint32_t flags;
/* These are return values. Some of them can be set by the caller, but
@ -303,35 +303,37 @@ struct radeon_surf {
* changed by the calculator.
*/
uint64_t bo_size;
uint64_t bo_alignment;
uint32_t bo_alignment;
/* This applies to EG and later. */
uint32_t bankw;
uint32_t bankh;
uint32_t mtilea;
uint32_t tile_split;
uint32_t stencil_tile_split;
struct radeon_surf_level level[RADEON_SURF_MAX_LEVEL];
struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVEL];
uint32_t tiling_index[RADEON_SURF_MAX_LEVEL];
uint32_t stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
uint32_t pipe_config;
uint32_t num_banks;
uint32_t macro_tile_index;
uint32_t micro_tile_mode; /* displayable, thin, depth, rotated */
unsigned bankw:4; /* max 8 */
unsigned bankh:4; /* max 8 */
unsigned mtilea:4; /* max 8 */
unsigned tile_split:13; /* max 4K */
unsigned stencil_tile_split:13; /* max 4K */
unsigned pipe_config:5; /* max 17 */
unsigned num_banks:5; /* max 16 */
unsigned macro_tile_index:4; /* max 15 */
unsigned micro_tile_mode:3; /* displayable, thin, depth, rotated */
/* Whether the depth miptree or stencil miptree as used by the DB are
* adjusted from their TC compatible form to ensure depth/stencil
* compatibility. If either is true, the corresponding plane cannot be
* sampled from.
*/
bool depth_adjusted;
bool stencil_adjusted;
unsigned depth_adjusted:1;
unsigned stencil_adjusted:1;
struct radeon_surf_level level[RADEON_SURF_MAX_LEVELS];
struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVELS];
uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];
uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
uint64_t dcc_size;
uint64_t dcc_alignment;
uint32_t dcc_alignment;
/* TC-compatible HTILE only. */
uint64_t htile_size;
uint64_t htile_alignment;
uint32_t htile_alignment;
};
struct radeon_bo_list_item {

4
src/gallium/winsys/radeon/drm/radeon_drm_surface.c
View File

@ -161,7 +161,7 @@ static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
surf_drm->tile_split = surf_ws->tile_split;
surf_drm->stencil_tile_split = surf_ws->stencil_tile_split;
for (i = 0; i < RADEON_SURF_MAX_LEVEL; i++) {
for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->level[i]);
surf_level_winsys_to_drm(&surf_drm->stencil_level[i],
&surf_ws->stencil_level[i]);
@ -195,7 +195,7 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
surf_ws->macro_tile_index = cik_get_macro_tile_index(surf_ws);
for (i = 0; i < RADEON_SURF_MAX_LEVEL; i++) {
for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
surf_level_drm_to_winsys(&surf_ws->level[i], &surf_drm->level[i]);
surf_level_drm_to_winsys(&surf_ws->stencil_level[i],
&surf_drm->stencil_level[i]);