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nouveau: Handle unaligned tlsBase during spills 

Without this, 128-bit or 64-bit register spills can generate unaligned
loads and stores if tlsBase is unaligned.

Fixes glsl-1.50/execution/variable-indexing/gs-input-array-vec3-index-rd
with NV50_PROG_USE_NIR=1 on kepler

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13693>
This commit is contained in:
M Henning 2021-11-06 21:33:34 -04:00 committed by Marge Bot
parent 4de13d53fe
commit d12e16fc3b
1 changed files with 8 additions and 2 deletions
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10
src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
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@ -1645,8 +1645,14 @@ SpillCodeInserter::assignSlot(const Interval &livei, const unsigned int size)
int32_t offset;
std::list<SpillSlot>::iterator pos = slots.end(), it = slots.begin();
if (offsetBase % size)
offsetBase += size - (offsetBase % size);
if (!func->stackPtr) {
// Later, we compute the address as (offsetBase + tlsBase)
// tlsBase might not be size-aligned, so we add just enough
// to give the final address the correct alignment
offsetBase = align(offsetBase + func->tlsBase, size) - func->tlsBase;
} else {
offsetBase = align(offsetBase, size);
}
slot.sym = NULL;