From d12e16fc3b5217613aa077f5f3418f16cf5cb824 Mon Sep 17 00:00:00 2001
From: M Henning <drawoc@darkrefraction.com>
Date: Sat, 6 Nov 2021 21:33:34 -0400
Subject: [PATCH] nouveau: Handle unaligned tlsBase during spills

Without this, 128-bit or 64-bit register spills can generate unaligned
loads and stores if tlsBase is unaligned.

Fixes glsl-1.50/execution/variable-indexing/gs-input-array-vec3-index-rd
with NV50_PROG_USE_NIR=1 on kepler

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13693>
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index b18a7a86fa8..b351ad7ae51 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -1645,8 +1645,14 @@ SpillCodeInserter::assignSlot(const Interval &livei, const unsigned int size)
    int32_t offset;
    std::list<SpillSlot>::iterator pos = slots.end(), it = slots.begin();
 
-   if (offsetBase % size)
-      offsetBase += size - (offsetBase % size);
+   if (!func->stackPtr) {
+      // Later, we compute the address as (offsetBase + tlsBase)
+      // tlsBase might not be size-aligned, so we add just enough
+      // to give the final address the correct alignment
+      offsetBase = align(offsetBase + func->tlsBase, size) - func->tlsBase;
+   } else {
+      offsetBase = align(offsetBase, size);
+   }
 
    slot.sym = NULL;