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i965/vec4: Send from GRF in atomic operations. 

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Matt Turner 2015-10-30 10:07:23 -07:00
parent 3b37155a68
commit cf3121ed18
1 changed files with 18 additions and 12 deletions
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30
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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@ -1183,24 +1183,27 @@ vec4_visitor::gs_end_primitive()
void void
vec4_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index, vec4_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
dst_reg dst, src_reg offset, dst_reg dst, src_reg surf_offset,
src_reg src0, src_reg src1) src_reg src0, src_reg src1)
{ {
unsigned mlen = 0; unsigned mlen = 1 + (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
src_reg src_payload(this, glsl_type::uint_type, mlen);
dst_reg payload(src_payload);
payload.writemask = WRITEMASK_X;
/* Set the atomic operation offset. */ /* Set the atomic operation offset. */
emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen, 0), WRITEMASK_X), offset)); emit(MOV(offset(payload, 0), surf_offset));
mlen++; unsigned i = 1;
/* Set the atomic operation arguments. */ /* Set the atomic operation arguments. */
if (src0.file != BAD_FILE) { if (src0.file != BAD_FILE) {
emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen, 0), WRITEMASK_X), src0)); emit(MOV(offset(payload, i), src0));
mlen++; i++;
} }
if (src1.file != BAD_FILE) { if (src1.file != BAD_FILE) {
emit(MOV(brw_writemask(brw_uvec_mrf(8, mlen, 0), WRITEMASK_X), src1)); emit(MOV(offset(payload, i), src1));
mlen++; i++;
} }
/* Emit the instruction. Note that this maps to the normal SIMD8 /* Emit the instruction. Note that this maps to the normal SIMD8
@ -1208,24 +1211,27 @@ vec4_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
* unused channels will be masked out. * unused channels will be masked out.
*/ */
vec4_instruction *inst = emit(SHADER_OPCODE_UNTYPED_ATOMIC, dst, vec4_instruction *inst = emit(SHADER_OPCODE_UNTYPED_ATOMIC, dst,
brw_message_reg(0), src_payload,
src_reg(surf_index), src_reg(atomic_op)); src_reg(surf_index), src_reg(atomic_op));
inst->mlen = mlen; inst->mlen = mlen;
} }
void void
vec4_visitor::emit_untyped_surface_read(unsigned surf_index, dst_reg dst, vec4_visitor::emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
src_reg offset) src_reg surf_offset)
{ {
dst_reg offset(this, glsl_type::uint_type);
offset.writemask = WRITEMASK_X;
/* Set the surface read offset. */ /* Set the surface read offset. */
emit(MOV(brw_writemask(brw_uvec_mrf(8, 0, 0), WRITEMASK_X), offset)); emit(MOV(offset, surf_offset));
/* Emit the instruction. Note that this maps to the normal SIMD8 /* Emit the instruction. Note that this maps to the normal SIMD8
* untyped surface read message, but that's OK because unused * untyped surface read message, but that's OK because unused
* channels will be masked out. * channels will be masked out.
*/ */
vec4_instruction *inst = emit(SHADER_OPCODE_UNTYPED_SURFACE_READ, dst, vec4_instruction *inst = emit(SHADER_OPCODE_UNTYPED_SURFACE_READ, dst,
brw_message_reg(0), src_reg(offset),
src_reg(surf_index), src_reg(1)); src_reg(surf_index), src_reg(1));
inst->mlen = 1; inst->mlen = 1;
} }