From ce1d72609d4e6f020373fde914d83c4427b7d9ad Mon Sep 17 00:00:00 2001 From: Sonny Jiang Date: Wed, 3 Oct 2018 11:53:13 -0400 Subject: [PATCH] radeonsi:optimizing SET_CONTEXT_REG for shaders Tessellation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Sonny Jiang Signed-off-by: Marek Olšák --- src/gallium/drivers/radeonsi/si_gfx_cs.c | 1 + src/gallium/drivers/radeonsi/si_shader.h | 3 +++ src/gallium/drivers/radeonsi/si_state.h | 1 + .../drivers/radeonsi/si_state_shaders.c | 26 +++++++++++++++---- 4 files changed, 26 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index 5f1c6987009..532a6365bf1 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -376,6 +376,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx) ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_Z_FORMAT] = 0x00000000; ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_COL_FORMAT] = 0x00000000; ctx->tracked_regs.reg_value[SI_TRACKED_CB_SHADER_MASK] = 0xffffffff; + ctx->tracked_regs.reg_value[SI_TRACKED_VGT_TF_PARAM] = 0x00000000; /* Set all saved registers state to saved. */ ctx->tracked_regs.reg_saved = 0xffffffffffffffff; diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h index 109c70a9f91..49b1ccd5823 100644 --- a/src/gallium/drivers/radeonsi/si_shader.h +++ b/src/gallium/drivers/radeonsi/si_shader.h @@ -686,6 +686,9 @@ struct si_shader { unsigned cb_shader_mask; } ps; } ctx_reg; + + /*For save precompute registers value */ + unsigned vgt_tf_param; /* VGT_TF_PARAM */ }; struct si_shader_part { diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index 878b67f0ed3..54b03e0992f 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -312,6 +312,7 @@ enum si_tracked_reg { SI_TRACKED_SPI_SHADER_COL_FORMAT, SI_TRACKED_CB_SHADER_MASK, + SI_TRACKED_VGT_TF_PARAM, SI_NUM_TRACKED_REGS, }; diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index b074214bbd3..e493f991a1b 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -396,11 +396,11 @@ static void si_set_tesseval_regs(struct si_screen *sscreen, } else distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST; - si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM, - S_028B6C_TYPE(type) | - S_028B6C_PARTITIONING(partitioning) | - S_028B6C_TOPOLOGY(topology) | - S_028B6C_DISTRIBUTION_MODE(distribution_mode)); + assert(pm4->shader); + pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) | + S_028B6C_PARTITIONING(partitioning) | + S_028B6C_TOPOLOGY(topology) | + S_028B6C_DISTRIBUTION_MODE(distribution_mode); } /* Polaris needs different VTX_REUSE_DEPTH settings depending on @@ -568,6 +568,12 @@ static void si_emit_shader_es(struct si_context *sctx) radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE, SI_TRACKED_VGT_ESGS_RING_ITEMSIZE, shader->selector->esgs_itemsize / 4); + + if (shader->selector->type == PIPE_SHADER_TESS_EVAL) + radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, + SI_TRACKED_VGT_TF_PARAM, + shader->vgt_tf_param); + } static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader) @@ -802,6 +808,11 @@ static void si_emit_shader_gs(struct si_context *sctx) radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE, SI_TRACKED_VGT_ESGS_RING_ITEMSIZE, shader->ctx_reg.gs.vgt_esgs_ring_itemsize); + + if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL) + radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, + SI_TRACKED_VGT_TF_PARAM, + shader->vgt_tf_param); } } @@ -965,6 +976,11 @@ static void si_emit_shader_vs(struct si_context *sctx) radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL, shader->ctx_reg.vs.pa_cl_vte_cntl); + + if (shader->selector->type == PIPE_SHADER_TESS_EVAL) + radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, + SI_TRACKED_VGT_TF_PARAM, + shader->vgt_tf_param); } /**