radeonsi/gfx10: fix tessellation for the legacy pipeline
ported from PAL Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
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@ -1308,6 +1308,16 @@ static void si_emit_shader_vs(struct si_context *sctx)
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if (initial_cdw != sctx->gfx_cs->current.cdw)
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if (initial_cdw != sctx->gfx_cs->current.cdw)
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sctx->context_roll = true;
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sctx->context_roll = true;
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/* Required programming for tessellation. (legacy pipeline only) */
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if (sctx->chip_class == GFX10 &&
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shader->selector->type == PIPE_SHADER_TESS_EVAL) {
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radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
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SI_TRACKED_VGT_GS_ONCHIP_CNTL,
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S_028A44_ES_VERTS_PER_SUBGRP(250) |
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S_028A44_GS_PRIMS_PER_SUBGRP(126) |
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S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
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}
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}
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}
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/**
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/**
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