ac: add has_distributed_tess to ac_gpu_info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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@ -447,6 +447,9 @@ bool ac_query_gpu_info(int fd, void *dev_p,
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*/
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info->has_clear_state = info->chip_class >= GFX7;
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info->has_distributed_tess = info->chip_class >= GFX8 &&
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info->max_se >= 2;
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/* Get the number of good compute units. */
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info->num_good_compute_units = 0;
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for (i = 0; i < info->max_se; i++)
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@ -59,6 +59,7 @@ struct radeon_info {
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uint32_t clock_crystal_freq;
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uint32_t tcc_cache_line_size;
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bool has_clear_state;
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bool has_distributed_tess;
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/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
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/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
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@ -2005,9 +2005,6 @@ VkResult radv_CreateDevice(
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device->tess_offchip_block_dw_size =
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device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
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device->has_distributed_tess =
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device->physical_device->rad_info.chip_class >= GFX8 &&
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device->physical_device->rad_info.max_se >= 2;
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if (getenv("RADV_TRACE_FILE")) {
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const char *filename = getenv("RADV_TRACE_FILE");
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@ -2010,7 +2010,7 @@ calculate_tess_state(struct radv_pipeline *pipeline,
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else
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topology = V_028B6C_OUTPUT_TRIANGLE_CW;
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if (pipeline->device->has_distributed_tess) {
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if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
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if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
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pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
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distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
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@ -4378,7 +4378,7 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
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radv_pipeline_has_gs(pipeline))
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ia_multi_vgt_param.partial_vs_wave = true;
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/* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
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if (device->has_distributed_tess) {
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if (device->physical_device->rad_info.has_distributed_tess) {
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if (radv_pipeline_has_gs(pipeline)) {
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if (device->physical_device->rad_info.chip_class <= GFX8)
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ia_multi_vgt_param.partial_es_wave = true;
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@ -704,7 +704,6 @@ struct radv_device {
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struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
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bool always_use_syncobj;
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bool has_distributed_tess;
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bool pbb_allowed;
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bool dfsm_allowed;
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uint32_t tess_offchip_block_dw_size;
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@ -1109,10 +1109,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
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S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
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}
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sscreen->has_distributed_tess =
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sscreen->info.chip_class >= GFX8 &&
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sscreen->info.max_se >= 2;
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sscreen->has_draw_indirect_multi =
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(sscreen->info.family >= CHIP_POLARIS10) ||
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(sscreen->info.chip_class == GFX8 &&
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@ -491,7 +491,6 @@ struct si_screen {
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unsigned eqaa_force_coverage_samples;
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unsigned eqaa_force_z_samples;
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unsigned eqaa_force_color_samples;
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bool has_distributed_tess;
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bool has_draw_indirect_multi;
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bool has_out_of_order_rast;
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bool assume_no_z_fights;
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@ -175,7 +175,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
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/* When distributed tessellation is unsupported, switch between SEs
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* at a higher frequency to compensate for it.
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*/
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if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1)
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if (!sctx->screen->info.has_distributed_tess && sctx->screen->info.max_se > 1)
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*num_patches = MIN2(*num_patches, 16); /* recommended */
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/* Make sure that vector lanes are reasonably occupied. It probably
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@ -363,7 +363,7 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen,
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partial_vs_wave = true;
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/* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
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if (sscreen->has_distributed_tess) {
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if (sscreen->info.has_distributed_tess) {
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if (key->u.uses_gs) {
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if (sscreen->info.chip_class == GFX8)
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partial_es_wave = true;
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@ -382,7 +382,7 @@ static void si_set_tesseval_regs(struct si_screen *sscreen,
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else
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topology = V_028B6C_OUTPUT_TRIANGLE_CW;
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if (sscreen->has_distributed_tess) {
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if (sscreen->info.has_distributed_tess) {
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if (sscreen->info.family == CHIP_FIJI ||
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sscreen->info.family >= CHIP_POLARIS10)
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distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
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