From c08401f0353e941691a5f40945cbdd04030a94c7 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 2 Aug 2019 12:13:20 +0200 Subject: [PATCH] ac: add has_distributed_tess to ac_gpu_info MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák --- src/amd/common/ac_gpu_info.c | 3 +++ src/amd/common/ac_gpu_info.h | 1 + src/amd/vulkan/radv_device.c | 3 --- src/amd/vulkan/radv_pipeline.c | 4 ++-- src/amd/vulkan/radv_private.h | 1 - src/gallium/drivers/radeonsi/si_pipe.c | 4 ---- src/gallium/drivers/radeonsi/si_pipe.h | 1 - src/gallium/drivers/radeonsi/si_state_draw.c | 4 ++-- src/gallium/drivers/radeonsi/si_state_shaders.c | 2 +- 9 files changed, 9 insertions(+), 14 deletions(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index ed6e273c598..a3f1afe1f04 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -447,6 +447,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, */ info->has_clear_state = info->chip_class >= GFX7; + info->has_distributed_tess = info->chip_class >= GFX8 && + info->max_se >= 2; + /* Get the number of good compute units. */ info->num_good_compute_units = 0; for (i = 0; i < info->max_se; i++) diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 69bac7252bf..9ce1650c03c 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -59,6 +59,7 @@ struct radeon_info { uint32_t clock_crystal_freq; uint32_t tcc_cache_line_size; bool has_clear_state; + bool has_distributed_tess; /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index ca484fcc0fc..ad5c104f44f 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -2005,9 +2005,6 @@ VkResult radv_CreateDevice( device->tess_offchip_block_dw_size = device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192; - device->has_distributed_tess = - device->physical_device->rad_info.chip_class >= GFX8 && - device->physical_device->rad_info.max_se >= 2; if (getenv("RADV_TRACE_FILE")) { const char *filename = getenv("RADV_TRACE_FILE"); diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index e43b77b192e..584dddb48df 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2010,7 +2010,7 @@ calculate_tess_state(struct radv_pipeline *pipeline, else topology = V_028B6C_OUTPUT_TRIANGLE_CW; - if (pipeline->device->has_distributed_tess) { + if (pipeline->device->physical_device->rad_info.has_distributed_tess) { if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI || pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10) distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS; @@ -4378,7 +4378,7 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline, radv_pipeline_has_gs(pipeline)) ia_multi_vgt_param.partial_vs_wave = true; /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */ - if (device->has_distributed_tess) { + if (device->physical_device->rad_info.has_distributed_tess) { if (radv_pipeline_has_gs(pipeline)) { if (device->physical_device->rad_info.chip_class <= GFX8) ia_multi_vgt_param.partial_es_wave = true; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 39d349b723c..287c2abfa3f 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -704,7 +704,6 @@ struct radv_device { struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES]; bool always_use_syncobj; - bool has_distributed_tess; bool pbb_allowed; bool dfsm_allowed; uint32_t tess_offchip_block_dw_size; diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 21e785dd44f..b6fce0640f4 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1109,10 +1109,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws, S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers); } - sscreen->has_distributed_tess = - sscreen->info.chip_class >= GFX8 && - sscreen->info.max_se >= 2; - sscreen->has_draw_indirect_multi = (sscreen->info.family >= CHIP_POLARIS10) || (sscreen->info.chip_class == GFX8 && diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 4630fff7357..6b0b5d3e20d 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -491,7 +491,6 @@ struct si_screen { unsigned eqaa_force_coverage_samples; unsigned eqaa_force_z_samples; unsigned eqaa_force_color_samples; - bool has_distributed_tess; bool has_draw_indirect_multi; bool has_out_of_order_rast; bool assume_no_z_fights; diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 118d87e4734..dd4b13fe97f 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -175,7 +175,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx, /* When distributed tessellation is unsupported, switch between SEs * at a higher frequency to compensate for it. */ - if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1) + if (!sctx->screen->info.has_distributed_tess && sctx->screen->info.max_se > 1) *num_patches = MIN2(*num_patches, 16); /* recommended */ /* Make sure that vector lanes are reasonably occupied. It probably @@ -363,7 +363,7 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen, partial_vs_wave = true; /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */ - if (sscreen->has_distributed_tess) { + if (sscreen->info.has_distributed_tess) { if (key->u.uses_gs) { if (sscreen->info.chip_class == GFX8) partial_es_wave = true; diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 8934e06ed9a..003d116e8eb 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -382,7 +382,7 @@ static void si_set_tesseval_regs(struct si_screen *sscreen, else topology = V_028B6C_OUTPUT_TRIANGLE_CW; - if (sscreen->has_distributed_tess) { + if (sscreen->info.has_distributed_tess) { if (sscreen->info.family == CHIP_FIJI || sscreen->info.family >= CHIP_POLARIS10) distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;