iris: Add an iris_is_domain_l3_coherent helper.
The render, depth, sampler, and data (HDC) caches are all coherent with L3. We consider OTHER_READ and OTHER_WRITE to be non-coherent, as they're kitchen-sink domains which include non-L3-clients. Starting with Tigerlake, the VF cache is coherent with L3 (because we set the L3BypassDisable bit in the vertex/index buffer packets). Reviewed-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Rohan Garg <rohan.garg@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15275>
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@ -36,6 +36,7 @@
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#include "util/simple_mtx.h"
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#include "pipe/p_defines.h"
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#include "pipebuffer/pb_slab.h"
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#include "intel/dev/intel_device_info.h"
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struct intel_device_info;
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struct util_debug_callback;
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@ -115,7 +116,7 @@ enum iris_domain {
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IRIS_DOMAIN_SAMPLER_READ,
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/** Pull-style shader constant loads. */
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IRIS_DOMAIN_PULL_CONSTANT_READ,
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/** Any other read-only cache. */
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/** Any other read-only cache, including reads from non-L3 clients. */
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IRIS_DOMAIN_OTHER_READ,
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/** Number of caching domains. */
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NUM_IRIS_DOMAINS,
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@ -133,6 +134,20 @@ iris_domain_is_read_only(enum iris_domain access)
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access <= IRIS_DOMAIN_OTHER_READ;
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}
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static inline bool
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iris_domain_is_l3_coherent(const struct intel_device_info *devinfo,
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enum iris_domain access)
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{
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/* VF reads are coherent with the L3 on Tigerlake+ because we set
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* the "L3 Bypass Disable" bit in the vertex/index buffer packets.
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*/
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if (access == IRIS_DOMAIN_VF_READ)
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return devinfo->ver >= 12;
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return access != IRIS_DOMAIN_OTHER_WRITE &&
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access != IRIS_DOMAIN_OTHER_READ;
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}
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enum iris_mmap_mode {
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IRIS_MMAP_NONE, /**< Cannot be mapped */
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IRIS_MMAP_UC, /**< Fully uncached memory map */
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