From b92cd585081f7d04f7fe3855d46ebce534090dab Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 2 Aug 2021 12:47:10 -0700 Subject: [PATCH] iris: Add an iris_is_domain_l3_coherent helper. The render, depth, sampler, and data (HDC) caches are all coherent with L3. We consider OTHER_READ and OTHER_WRITE to be non-coherent, as they're kitchen-sink domains which include non-L3-clients. Starting with Tigerlake, the VF cache is coherent with L3 (because we set the L3BypassDisable bit in the vertex/index buffer packets). Reviewed-by: Francisco Jerez Reviewed-by: Rohan Garg Part-of: --- src/gallium/drivers/iris/iris_bufmgr.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/iris/iris_bufmgr.h b/src/gallium/drivers/iris/iris_bufmgr.h index 89a2e993aab..97701541600 100644 --- a/src/gallium/drivers/iris/iris_bufmgr.h +++ b/src/gallium/drivers/iris/iris_bufmgr.h @@ -36,6 +36,7 @@ #include "util/simple_mtx.h" #include "pipe/p_defines.h" #include "pipebuffer/pb_slab.h" +#include "intel/dev/intel_device_info.h" struct intel_device_info; struct util_debug_callback; @@ -115,7 +116,7 @@ enum iris_domain { IRIS_DOMAIN_SAMPLER_READ, /** Pull-style shader constant loads. */ IRIS_DOMAIN_PULL_CONSTANT_READ, - /** Any other read-only cache. */ + /** Any other read-only cache, including reads from non-L3 clients. */ IRIS_DOMAIN_OTHER_READ, /** Number of caching domains. */ NUM_IRIS_DOMAINS, @@ -133,6 +134,20 @@ iris_domain_is_read_only(enum iris_domain access) access <= IRIS_DOMAIN_OTHER_READ; } +static inline bool +iris_domain_is_l3_coherent(const struct intel_device_info *devinfo, + enum iris_domain access) +{ + /* VF reads are coherent with the L3 on Tigerlake+ because we set + * the "L3 Bypass Disable" bit in the vertex/index buffer packets. + */ + if (access == IRIS_DOMAIN_VF_READ) + return devinfo->ver >= 12; + + return access != IRIS_DOMAIN_OTHER_WRITE && + access != IRIS_DOMAIN_OTHER_READ; +} + enum iris_mmap_mode { IRIS_MMAP_NONE, /**< Cannot be mapped */ IRIS_MMAP_UC, /**< Fully uncached memory map */