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iris: Add an iris_is_domain_l3_coherent helper. 

The render, depth, sampler, and data (HDC) caches are all coherent
with L3.  We consider OTHER_READ and OTHER_WRITE to be non-coherent,
as they're kitchen-sink domains which include non-L3-clients.

Starting with Tigerlake, the VF cache is coherent with L3 (because we
set the L3BypassDisable bit in the vertex/index buffer packets).

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15275>
This commit is contained in:
Kenneth Graunke 2021-08-02 12:47:10 -07:00 committed by Marge Bot
parent 536eee31d0
commit b92cd58508
1 changed files with 16 additions and 1 deletions
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17
src/gallium/drivers/iris/iris_bufmgr.h
View File

@ -36,6 +36,7 @@
#include "util/simple_mtx.h"
#include "pipe/p_defines.h"
#include "pipebuffer/pb_slab.h"
#include "intel/dev/intel_device_info.h"
struct intel_device_info;
struct util_debug_callback;
@ -115,7 +116,7 @@ enum iris_domain {
IRIS_DOMAIN_SAMPLER_READ,
/** Pull-style shader constant loads. */
IRIS_DOMAIN_PULL_CONSTANT_READ,
/** Any other read-only cache. */
/** Any other read-only cache, including reads from non-L3 clients. */
IRIS_DOMAIN_OTHER_READ,
/** Number of caching domains. */
NUM_IRIS_DOMAINS,
@ -133,6 +134,20 @@ iris_domain_is_read_only(enum iris_domain access)
access <= IRIS_DOMAIN_OTHER_READ;
}
static inline bool
iris_domain_is_l3_coherent(const struct intel_device_info *devinfo,
enum iris_domain access)
{
/* VF reads are coherent with the L3 on Tigerlake+ because we set
* the "L3 Bypass Disable" bit in the vertex/index buffer packets.
*/
if (access == IRIS_DOMAIN_VF_READ)
return devinfo->ver >= 12;
return access != IRIS_DOMAIN_OTHER_WRITE &&
access != IRIS_DOMAIN_OTHER_READ;
}
enum iris_mmap_mode {
IRIS_MMAP_NONE, /**< Cannot be mapped */
IRIS_MMAP_UC, /**< Fully uncached memory map */