gallium/radeon: move pre-GFX9 radeon_bo_metadata.* to u.legacy.*
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
parent
9b365d497a
commit
b25d7c2cbf
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@ -1132,9 +1132,9 @@ r300_texture_create_object(struct r300_screen *rscreen,
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util_format_is_depth_or_stencil(base->format) ? "depth" : "color");
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util_format_is_depth_or_stencil(base->format) ? "depth" : "color");
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}
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}
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tiling.microtile = tex->tex.microtile;
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tiling.u.legacy.microtile = tex->tex.microtile;
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tiling.macrotile = tex->tex.macrotile[0];
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tiling.u.legacy.macrotile = tex->tex.macrotile[0];
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tiling.stride = tex->tex.stride_in_bytes[0];
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tiling.u.legacy.stride = tex->tex.stride_in_bytes[0];
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rws->buffer_set_metadata(tex->buf, &tiling);
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rws->buffer_set_metadata(tex->buf, &tiling);
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return tex;
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return tex;
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@ -1195,20 +1195,20 @@ struct pipe_resource *r300_texture_from_handle(struct pipe_screen *screen,
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/* Enforce a microtiled zbuffer. */
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/* Enforce a microtiled zbuffer. */
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if (util_format_is_depth_or_stencil(base->format) &&
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if (util_format_is_depth_or_stencil(base->format) &&
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tiling.microtile == RADEON_LAYOUT_LINEAR) {
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tiling.u.legacy.microtile == RADEON_LAYOUT_LINEAR) {
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switch (util_format_get_blocksize(base->format)) {
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switch (util_format_get_blocksize(base->format)) {
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case 4:
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case 4:
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tiling.microtile = RADEON_LAYOUT_TILED;
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tiling.u.legacy.microtile = RADEON_LAYOUT_TILED;
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break;
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break;
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case 2:
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case 2:
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tiling.microtile = RADEON_LAYOUT_SQUARETILED;
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tiling.u.legacy.microtile = RADEON_LAYOUT_SQUARETILED;
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break;
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break;
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}
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}
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}
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}
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return (struct pipe_resource*)
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return (struct pipe_resource*)
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r300_texture_create_object(rscreen, base, tiling.microtile, tiling.macrotile,
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r300_texture_create_object(rscreen, base, tiling.u.legacy.microtile, tiling.u.legacy.macrotile,
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stride, buffer);
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stride, buffer);
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}
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}
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@ -281,24 +281,29 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
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return 0;
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return 0;
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}
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}
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static void r600_texture_init_metadata(struct r600_texture *rtex,
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static void r600_texture_init_metadata(struct r600_common_screen *rscreen,
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struct r600_texture *rtex,
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struct radeon_bo_metadata *metadata)
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struct radeon_bo_metadata *metadata)
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{
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{
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struct radeon_surf *surface = &rtex->surface;
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struct radeon_surf *surface = &rtex->surface;
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memset(metadata, 0, sizeof(*metadata));
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memset(metadata, 0, sizeof(*metadata));
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metadata->microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
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RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
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if (rscreen->chip_class >= GFX9) {
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metadata->macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
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} else {
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RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
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metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
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metadata->pipe_config = surface->u.legacy.pipe_config;
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RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
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metadata->bankw = surface->u.legacy.bankw;
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metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
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metadata->bankh = surface->u.legacy.bankh;
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RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
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metadata->tile_split = surface->u.legacy.tile_split;
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metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
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metadata->mtilea = surface->u.legacy.mtilea;
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metadata->u.legacy.bankw = surface->u.legacy.bankw;
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metadata->num_banks = surface->u.legacy.num_banks;
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metadata->u.legacy.bankh = surface->u.legacy.bankh;
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metadata->stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
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metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
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metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
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metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
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metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
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metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
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metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
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}
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}
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}
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static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
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static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
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@ -526,7 +531,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
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/* Set metadata. */
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/* Set metadata. */
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if (!res->is_shared || update_metadata) {
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if (!res->is_shared || update_metadata) {
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r600_texture_init_metadata(rtex, &metadata);
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r600_texture_init_metadata(rscreen, rtex, &metadata);
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if (rscreen->query_opaque_metadata)
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if (rscreen->query_opaque_metadata)
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rscreen->query_opaque_metadata(rscreen, rtex,
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rscreen->query_opaque_metadata(rscreen, rtex,
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&metadata);
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&metadata);
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@ -1265,22 +1270,25 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen
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rscreen->ws->buffer_get_metadata(buf, &metadata);
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rscreen->ws->buffer_get_metadata(buf, &metadata);
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surface.u.legacy.pipe_config = metadata.pipe_config;
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if (rscreen->chip_class >= GFX9) {
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surface.u.legacy.bankw = metadata.bankw;
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} else {
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surface.u.legacy.bankh = metadata.bankh;
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surface.u.legacy.pipe_config = metadata.u.legacy.pipe_config;
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surface.u.legacy.tile_split = metadata.tile_split;
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surface.u.legacy.bankw = metadata.u.legacy.bankw;
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surface.u.legacy.mtilea = metadata.mtilea;
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surface.u.legacy.bankh = metadata.u.legacy.bankh;
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surface.u.legacy.num_banks = metadata.num_banks;
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surface.u.legacy.tile_split = metadata.u.legacy.tile_split;
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surface.u.legacy.mtilea = metadata.u.legacy.mtilea;
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surface.u.legacy.num_banks = metadata.u.legacy.num_banks;
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if (metadata.macrotile == RADEON_LAYOUT_TILED)
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if (metadata.u.legacy.macrotile == RADEON_LAYOUT_TILED)
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array_mode = RADEON_SURF_MODE_2D;
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array_mode = RADEON_SURF_MODE_2D;
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else if (metadata.microtile == RADEON_LAYOUT_TILED)
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else if (metadata.u.legacy.microtile == RADEON_LAYOUT_TILED)
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array_mode = RADEON_SURF_MODE_1D;
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array_mode = RADEON_SURF_MODE_1D;
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else
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else
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array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
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array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
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}
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r = r600_init_surface(rscreen, &surface, templ, array_mode, stride,
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r = r600_init_surface(rscreen, &surface, templ, array_mode, stride,
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offset, true, metadata.scanout, false, false);
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offset, true, metadata.u.legacy.scanout, false, false);
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if (r) {
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if (r) {
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return NULL;
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return NULL;
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}
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}
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@ -237,16 +237,20 @@ struct radeon_bo_metadata {
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/* Tiling flags describing the texture layout for display code
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/* Tiling flags describing the texture layout for display code
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* and DRI sharing.
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* and DRI sharing.
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*/
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*/
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enum radeon_bo_layout microtile;
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union {
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enum radeon_bo_layout macrotile;
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struct {
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unsigned pipe_config;
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enum radeon_bo_layout microtile;
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unsigned bankw;
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enum radeon_bo_layout macrotile;
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unsigned bankh;
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unsigned pipe_config;
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unsigned tile_split;
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unsigned bankw;
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unsigned mtilea;
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unsigned bankh;
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unsigned num_banks;
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unsigned tile_split;
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unsigned stride;
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unsigned mtilea;
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bool scanout;
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unsigned num_banks;
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unsigned stride;
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bool scanout;
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} legacy;
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} u;
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/* Additional metadata associated with the buffer, in bytes.
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/* Additional metadata associated with the buffer, in bytes.
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* The maximum size is 64 * 4. This is opaque for the winsys & kernel.
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* The maximum size is 64 * 4. This is opaque for the winsys & kernel.
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@ -611,21 +611,24 @@ static void amdgpu_buffer_get_metadata(struct pb_buffer *_buf,
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tiling_flags = info.metadata.tiling_info;
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tiling_flags = info.metadata.tiling_info;
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md->microtile = RADEON_LAYOUT_LINEAR;
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if (bo->ws->info.chip_class >= GFX9) {
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md->macrotile = RADEON_LAYOUT_LINEAR;
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} else {
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md->u.legacy.microtile = RADEON_LAYOUT_LINEAR;
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md->u.legacy.macrotile = RADEON_LAYOUT_LINEAR;
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if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */
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if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */
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md->macrotile = RADEON_LAYOUT_TILED;
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md->u.legacy.macrotile = RADEON_LAYOUT_TILED;
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else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /* 1D_TILED_THIN1 */
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else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /* 1D_TILED_THIN1 */
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md->microtile = RADEON_LAYOUT_TILED;
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md->u.legacy.microtile = RADEON_LAYOUT_TILED;
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md->pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
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md->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
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md->bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
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md->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
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md->bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
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md->u.legacy.bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
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md->tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT));
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md->u.legacy.tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT));
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md->mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
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md->u.legacy.mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
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md->num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
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md->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
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md->scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /* DISPLAY */
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md->u.legacy.scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /* DISPLAY */
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}
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md->size_metadata = info.metadata.size_metadata;
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md->size_metadata = info.metadata.size_metadata;
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memcpy(md->metadata, info.metadata.umd_metadata, sizeof(md->metadata));
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memcpy(md->metadata, info.metadata.umd_metadata, sizeof(md->metadata));
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@ -640,25 +643,28 @@ static void amdgpu_buffer_set_metadata(struct pb_buffer *_buf,
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assert(bo->bo && "must not be called for slab entries");
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assert(bo->bo && "must not be called for slab entries");
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if (md->macrotile == RADEON_LAYOUT_TILED)
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if (bo->ws->info.chip_class >= GFX9) {
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tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */
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} else {
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else if (md->microtile == RADEON_LAYOUT_TILED)
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if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
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tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */
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tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */
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else
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else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
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tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */
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tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */
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else
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tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */
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tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->pipe_config);
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tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->u.legacy.pipe_config);
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tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->bankw));
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tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->u.legacy.bankw));
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tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->bankh));
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tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->u.legacy.bankh));
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if (md->tile_split)
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if (md->u.legacy.tile_split)
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tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, eg_tile_split_rev(md->tile_split));
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tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, eg_tile_split_rev(md->u.legacy.tile_split));
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tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->mtilea));
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tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->u.legacy.mtilea));
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tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->num_banks)-1);
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tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->u.legacy.num_banks)-1);
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if (md->scanout)
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if (md->u.legacy.scanout)
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tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 0); /* DISPLAY_MICRO_TILING */
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tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 0); /* DISPLAY_MICRO_TILING */
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else
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else
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tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 1); /* THIN_MICRO_TILING */
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tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 1); /* THIN_MICRO_TILING */
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}
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metadata.tiling_info = tiling_flags;
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metadata.tiling_info = tiling_flags;
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metadata.size_metadata = md->size_metadata;
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metadata.size_metadata = md->size_metadata;
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@ -863,22 +863,22 @@ static void radeon_bo_get_metadata(struct pb_buffer *_buf,
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&args,
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&args,
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sizeof(args));
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sizeof(args));
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md->microtile = RADEON_LAYOUT_LINEAR;
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md->u.legacy.microtile = RADEON_LAYOUT_LINEAR;
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md->macrotile = RADEON_LAYOUT_LINEAR;
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md->u.legacy.macrotile = RADEON_LAYOUT_LINEAR;
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if (args.tiling_flags & RADEON_TILING_MICRO)
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if (args.tiling_flags & RADEON_TILING_MICRO)
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md->microtile = RADEON_LAYOUT_TILED;
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md->u.legacy.microtile = RADEON_LAYOUT_TILED;
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else if (args.tiling_flags & RADEON_TILING_MICRO_SQUARE)
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else if (args.tiling_flags & RADEON_TILING_MICRO_SQUARE)
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md->microtile = RADEON_LAYOUT_SQUARETILED;
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md->u.legacy.microtile = RADEON_LAYOUT_SQUARETILED;
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if (args.tiling_flags & RADEON_TILING_MACRO)
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if (args.tiling_flags & RADEON_TILING_MACRO)
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md->macrotile = RADEON_LAYOUT_TILED;
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md->u.legacy.macrotile = RADEON_LAYOUT_TILED;
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md->bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
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md->u.legacy.bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
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md->bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
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md->u.legacy.bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
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md->tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
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md->u.legacy.tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
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md->mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
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md->u.legacy.mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
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md->tile_split = eg_tile_split(md->tile_split);
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md->u.legacy.tile_split = eg_tile_split(md->u.legacy.tile_split);
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md->scanout = bo->rws->gen >= DRV_SI && !(args.tiling_flags & RADEON_TILING_R600_NO_SCANOUT);
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md->u.legacy.scanout = bo->rws->gen >= DRV_SI && !(args.tiling_flags & RADEON_TILING_R600_NO_SCANOUT);
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}
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}
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static void radeon_bo_set_metadata(struct pb_buffer *_buf,
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static void radeon_bo_set_metadata(struct pb_buffer *_buf,
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@ -893,31 +893,31 @@ static void radeon_bo_set_metadata(struct pb_buffer *_buf,
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os_wait_until_zero(&bo->num_active_ioctls, PIPE_TIMEOUT_INFINITE);
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os_wait_until_zero(&bo->num_active_ioctls, PIPE_TIMEOUT_INFINITE);
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||||||
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|
||||||
if (md->microtile == RADEON_LAYOUT_TILED)
|
if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
|
||||||
args.tiling_flags |= RADEON_TILING_MICRO;
|
args.tiling_flags |= RADEON_TILING_MICRO;
|
||||||
else if (md->microtile == RADEON_LAYOUT_SQUARETILED)
|
else if (md->u.legacy.microtile == RADEON_LAYOUT_SQUARETILED)
|
||||||
args.tiling_flags |= RADEON_TILING_MICRO_SQUARE;
|
args.tiling_flags |= RADEON_TILING_MICRO_SQUARE;
|
||||||
|
|
||||||
if (md->macrotile == RADEON_LAYOUT_TILED)
|
if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
|
||||||
args.tiling_flags |= RADEON_TILING_MACRO;
|
args.tiling_flags |= RADEON_TILING_MACRO;
|
||||||
|
|
||||||
args.tiling_flags |= (md->bankw & RADEON_TILING_EG_BANKW_MASK) <<
|
args.tiling_flags |= (md->u.legacy.bankw & RADEON_TILING_EG_BANKW_MASK) <<
|
||||||
RADEON_TILING_EG_BANKW_SHIFT;
|
RADEON_TILING_EG_BANKW_SHIFT;
|
||||||
args.tiling_flags |= (md->bankh & RADEON_TILING_EG_BANKH_MASK) <<
|
args.tiling_flags |= (md->u.legacy.bankh & RADEON_TILING_EG_BANKH_MASK) <<
|
||||||
RADEON_TILING_EG_BANKH_SHIFT;
|
RADEON_TILING_EG_BANKH_SHIFT;
|
||||||
if (md->tile_split) {
|
if (md->u.legacy.tile_split) {
|
||||||
args.tiling_flags |= (eg_tile_split_rev(md->tile_split) &
|
args.tiling_flags |= (eg_tile_split_rev(md->u.legacy.tile_split) &
|
||||||
RADEON_TILING_EG_TILE_SPLIT_MASK) <<
|
RADEON_TILING_EG_TILE_SPLIT_MASK) <<
|
||||||
RADEON_TILING_EG_TILE_SPLIT_SHIFT;
|
RADEON_TILING_EG_TILE_SPLIT_SHIFT;
|
||||||
}
|
}
|
||||||
args.tiling_flags |= (md->mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) <<
|
args.tiling_flags |= (md->u.legacy.mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) <<
|
||||||
RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
|
RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
|
||||||
|
|
||||||
if (bo->rws->gen >= DRV_SI && !md->scanout)
|
if (bo->rws->gen >= DRV_SI && !md->u.legacy.scanout)
|
||||||
args.tiling_flags |= RADEON_TILING_R600_NO_SCANOUT;
|
args.tiling_flags |= RADEON_TILING_R600_NO_SCANOUT;
|
||||||
|
|
||||||
args.handle = bo->handle;
|
args.handle = bo->handle;
|
||||||
args.pitch = md->stride;
|
args.pitch = md->u.legacy.stride;
|
||||||
|
|
||||||
drmCommandWriteRead(bo->rws->fd,
|
drmCommandWriteRead(bo->rws->fd,
|
||||||
DRM_RADEON_GEM_SET_TILING,
|
DRM_RADEON_GEM_SET_TILING,
|
||||||
|
|
Loading…
Reference in New Issue