From b25d7c2cbfaf0e3aadb3724bbf1a6cce218e6b2b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sun, 6 Nov 2016 14:51:57 +0100 Subject: [PATCH] gallium/radeon: move pre-GFX9 radeon_bo_metadata.* to u.legacy.* MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/r300/r300_texture.c | 14 ++-- src/gallium/drivers/radeon/r600_texture.c | 62 +++++++++-------- src/gallium/drivers/radeon/radeon_winsys.h | 24 ++++--- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 66 ++++++++++--------- src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 42 ++++++------ 5 files changed, 113 insertions(+), 95 deletions(-) diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index 32cbdcdb341..c202fbe9423 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -1132,9 +1132,9 @@ r300_texture_create_object(struct r300_screen *rscreen, util_format_is_depth_or_stencil(base->format) ? "depth" : "color"); } - tiling.microtile = tex->tex.microtile; - tiling.macrotile = tex->tex.macrotile[0]; - tiling.stride = tex->tex.stride_in_bytes[0]; + tiling.u.legacy.microtile = tex->tex.microtile; + tiling.u.legacy.macrotile = tex->tex.macrotile[0]; + tiling.u.legacy.stride = tex->tex.stride_in_bytes[0]; rws->buffer_set_metadata(tex->buf, &tiling); return tex; @@ -1195,20 +1195,20 @@ struct pipe_resource *r300_texture_from_handle(struct pipe_screen *screen, /* Enforce a microtiled zbuffer. */ if (util_format_is_depth_or_stencil(base->format) && - tiling.microtile == RADEON_LAYOUT_LINEAR) { + tiling.u.legacy.microtile == RADEON_LAYOUT_LINEAR) { switch (util_format_get_blocksize(base->format)) { case 4: - tiling.microtile = RADEON_LAYOUT_TILED; + tiling.u.legacy.microtile = RADEON_LAYOUT_TILED; break; case 2: - tiling.microtile = RADEON_LAYOUT_SQUARETILED; + tiling.u.legacy.microtile = RADEON_LAYOUT_SQUARETILED; break; } } return (struct pipe_resource*) - r300_texture_create_object(rscreen, base, tiling.microtile, tiling.macrotile, + r300_texture_create_object(rscreen, base, tiling.u.legacy.microtile, tiling.u.legacy.macrotile, stride, buffer); } diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index ece1e806e3e..353e942aaa2 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -281,24 +281,29 @@ static int r600_init_surface(struct r600_common_screen *rscreen, return 0; } -static void r600_texture_init_metadata(struct r600_texture *rtex, +static void r600_texture_init_metadata(struct r600_common_screen *rscreen, + struct r600_texture *rtex, struct radeon_bo_metadata *metadata) { struct radeon_surf *surface = &rtex->surface; memset(metadata, 0, sizeof(*metadata)); - metadata->microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ? - RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; - metadata->macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ? - RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; - metadata->pipe_config = surface->u.legacy.pipe_config; - metadata->bankw = surface->u.legacy.bankw; - metadata->bankh = surface->u.legacy.bankh; - metadata->tile_split = surface->u.legacy.tile_split; - metadata->mtilea = surface->u.legacy.mtilea; - metadata->num_banks = surface->u.legacy.num_banks; - metadata->stride = surface->u.legacy.level[0].nblk_x * surface->bpe; - metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0; + + if (rscreen->chip_class >= GFX9) { + } else { + metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ? + RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; + metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ? + RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; + metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config; + metadata->u.legacy.bankw = surface->u.legacy.bankw; + metadata->u.legacy.bankh = surface->u.legacy.bankh; + metadata->u.legacy.tile_split = surface->u.legacy.tile_split; + metadata->u.legacy.mtilea = surface->u.legacy.mtilea; + metadata->u.legacy.num_banks = surface->u.legacy.num_banks; + metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe; + metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0; + } } static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx, @@ -526,7 +531,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen, /* Set metadata. */ if (!res->is_shared || update_metadata) { - r600_texture_init_metadata(rtex, &metadata); + r600_texture_init_metadata(rscreen, rtex, &metadata); if (rscreen->query_opaque_metadata) rscreen->query_opaque_metadata(rscreen, rtex, &metadata); @@ -1265,22 +1270,25 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen rscreen->ws->buffer_get_metadata(buf, &metadata); - surface.u.legacy.pipe_config = metadata.pipe_config; - surface.u.legacy.bankw = metadata.bankw; - surface.u.legacy.bankh = metadata.bankh; - surface.u.legacy.tile_split = metadata.tile_split; - surface.u.legacy.mtilea = metadata.mtilea; - surface.u.legacy.num_banks = metadata.num_banks; + if (rscreen->chip_class >= GFX9) { + } else { + surface.u.legacy.pipe_config = metadata.u.legacy.pipe_config; + surface.u.legacy.bankw = metadata.u.legacy.bankw; + surface.u.legacy.bankh = metadata.u.legacy.bankh; + surface.u.legacy.tile_split = metadata.u.legacy.tile_split; + surface.u.legacy.mtilea = metadata.u.legacy.mtilea; + surface.u.legacy.num_banks = metadata.u.legacy.num_banks; - if (metadata.macrotile == RADEON_LAYOUT_TILED) - array_mode = RADEON_SURF_MODE_2D; - else if (metadata.microtile == RADEON_LAYOUT_TILED) - array_mode = RADEON_SURF_MODE_1D; - else - array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED; + if (metadata.u.legacy.macrotile == RADEON_LAYOUT_TILED) + array_mode = RADEON_SURF_MODE_2D; + else if (metadata.u.legacy.microtile == RADEON_LAYOUT_TILED) + array_mode = RADEON_SURF_MODE_1D; + else + array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED; + } r = r600_init_surface(rscreen, &surface, templ, array_mode, stride, - offset, true, metadata.scanout, false, false); + offset, true, metadata.u.legacy.scanout, false, false); if (r) { return NULL; } diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index bfc067d7639..e25f60cb904 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -237,16 +237,20 @@ struct radeon_bo_metadata { /* Tiling flags describing the texture layout for display code * and DRI sharing. */ - enum radeon_bo_layout microtile; - enum radeon_bo_layout macrotile; - unsigned pipe_config; - unsigned bankw; - unsigned bankh; - unsigned tile_split; - unsigned mtilea; - unsigned num_banks; - unsigned stride; - bool scanout; + union { + struct { + enum radeon_bo_layout microtile; + enum radeon_bo_layout macrotile; + unsigned pipe_config; + unsigned bankw; + unsigned bankh; + unsigned tile_split; + unsigned mtilea; + unsigned num_banks; + unsigned stride; + bool scanout; + } legacy; + } u; /* Additional metadata associated with the buffer, in bytes. * The maximum size is 64 * 4. This is opaque for the winsys & kernel. diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index c7dd1168f8b..15e5bce47ac 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -611,21 +611,24 @@ static void amdgpu_buffer_get_metadata(struct pb_buffer *_buf, tiling_flags = info.metadata.tiling_info; - md->microtile = RADEON_LAYOUT_LINEAR; - md->macrotile = RADEON_LAYOUT_LINEAR; + if (bo->ws->info.chip_class >= GFX9) { + } else { + md->u.legacy.microtile = RADEON_LAYOUT_LINEAR; + md->u.legacy.macrotile = RADEON_LAYOUT_LINEAR; - if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */ - md->macrotile = RADEON_LAYOUT_TILED; - else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /* 1D_TILED_THIN1 */ - md->microtile = RADEON_LAYOUT_TILED; + if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */ + md->u.legacy.macrotile = RADEON_LAYOUT_TILED; + else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /* 1D_TILED_THIN1 */ + md->u.legacy.microtile = RADEON_LAYOUT_TILED; - md->pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); - md->bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); - md->bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); - md->tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT)); - md->mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); - md->num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); - md->scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /* DISPLAY */ + md->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); + md->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); + md->u.legacy.bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); + md->u.legacy.tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT)); + md->u.legacy.mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); + md->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); + md->u.legacy.scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /* DISPLAY */ + } md->size_metadata = info.metadata.size_metadata; memcpy(md->metadata, info.metadata.umd_metadata, sizeof(md->metadata)); @@ -640,25 +643,28 @@ static void amdgpu_buffer_set_metadata(struct pb_buffer *_buf, assert(bo->bo && "must not be called for slab entries"); - if (md->macrotile == RADEON_LAYOUT_TILED) - tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */ - else if (md->microtile == RADEON_LAYOUT_TILED) - tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */ - else - tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */ + if (bo->ws->info.chip_class >= GFX9) { + } else { + if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED) + tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */ + else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED) + tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */ + else + tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */ - tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->pipe_config); - tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->bankw)); - tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->bankh)); - if (md->tile_split) - tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, eg_tile_split_rev(md->tile_split)); - tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->mtilea)); - tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->num_banks)-1); + tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->u.legacy.pipe_config); + tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->u.legacy.bankw)); + tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->u.legacy.bankh)); + if (md->u.legacy.tile_split) + tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, eg_tile_split_rev(md->u.legacy.tile_split)); + tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->u.legacy.mtilea)); + tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->u.legacy.num_banks)-1); - if (md->scanout) - tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 0); /* DISPLAY_MICRO_TILING */ - else - tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 1); /* THIN_MICRO_TILING */ + if (md->u.legacy.scanout) + tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 0); /* DISPLAY_MICRO_TILING */ + else + tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 1); /* THIN_MICRO_TILING */ + } metadata.tiling_info = tiling_flags; metadata.size_metadata = md->size_metadata; diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index f6d5c8a51c3..fe2aa90a0c9 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -863,22 +863,22 @@ static void radeon_bo_get_metadata(struct pb_buffer *_buf, &args, sizeof(args)); - md->microtile = RADEON_LAYOUT_LINEAR; - md->macrotile = RADEON_LAYOUT_LINEAR; + md->u.legacy.microtile = RADEON_LAYOUT_LINEAR; + md->u.legacy.macrotile = RADEON_LAYOUT_LINEAR; if (args.tiling_flags & RADEON_TILING_MICRO) - md->microtile = RADEON_LAYOUT_TILED; + md->u.legacy.microtile = RADEON_LAYOUT_TILED; else if (args.tiling_flags & RADEON_TILING_MICRO_SQUARE) - md->microtile = RADEON_LAYOUT_SQUARETILED; + md->u.legacy.microtile = RADEON_LAYOUT_SQUARETILED; if (args.tiling_flags & RADEON_TILING_MACRO) - md->macrotile = RADEON_LAYOUT_TILED; + md->u.legacy.macrotile = RADEON_LAYOUT_TILED; - md->bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; - md->bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; - md->tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; - md->mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; - md->tile_split = eg_tile_split(md->tile_split); - md->scanout = bo->rws->gen >= DRV_SI && !(args.tiling_flags & RADEON_TILING_R600_NO_SCANOUT); + md->u.legacy.bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; + md->u.legacy.bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; + md->u.legacy.tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; + md->u.legacy.mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; + md->u.legacy.tile_split = eg_tile_split(md->u.legacy.tile_split); + md->u.legacy.scanout = bo->rws->gen >= DRV_SI && !(args.tiling_flags & RADEON_TILING_R600_NO_SCANOUT); } static void radeon_bo_set_metadata(struct pb_buffer *_buf, @@ -893,31 +893,31 @@ static void radeon_bo_set_metadata(struct pb_buffer *_buf, os_wait_until_zero(&bo->num_active_ioctls, PIPE_TIMEOUT_INFINITE); - if (md->microtile == RADEON_LAYOUT_TILED) + if (md->u.legacy.microtile == RADEON_LAYOUT_TILED) args.tiling_flags |= RADEON_TILING_MICRO; - else if (md->microtile == RADEON_LAYOUT_SQUARETILED) + else if (md->u.legacy.microtile == RADEON_LAYOUT_SQUARETILED) args.tiling_flags |= RADEON_TILING_MICRO_SQUARE; - if (md->macrotile == RADEON_LAYOUT_TILED) + if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED) args.tiling_flags |= RADEON_TILING_MACRO; - args.tiling_flags |= (md->bankw & RADEON_TILING_EG_BANKW_MASK) << + args.tiling_flags |= (md->u.legacy.bankw & RADEON_TILING_EG_BANKW_MASK) << RADEON_TILING_EG_BANKW_SHIFT; - args.tiling_flags |= (md->bankh & RADEON_TILING_EG_BANKH_MASK) << + args.tiling_flags |= (md->u.legacy.bankh & RADEON_TILING_EG_BANKH_MASK) << RADEON_TILING_EG_BANKH_SHIFT; - if (md->tile_split) { - args.tiling_flags |= (eg_tile_split_rev(md->tile_split) & + if (md->u.legacy.tile_split) { + args.tiling_flags |= (eg_tile_split_rev(md->u.legacy.tile_split) & RADEON_TILING_EG_TILE_SPLIT_MASK) << RADEON_TILING_EG_TILE_SPLIT_SHIFT; } - args.tiling_flags |= (md->mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) << + args.tiling_flags |= (md->u.legacy.mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT; - if (bo->rws->gen >= DRV_SI && !md->scanout) + if (bo->rws->gen >= DRV_SI && !md->u.legacy.scanout) args.tiling_flags |= RADEON_TILING_R600_NO_SCANOUT; args.handle = bo->handle; - args.pitch = md->stride; + args.pitch = md->u.legacy.stride; drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_SET_TILING,