turnip: push constants
Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
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@ -1772,6 +1772,8 @@ tu_CmdPushConstants(VkCommandBuffer commandBuffer,
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uint32_t size,
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uint32_t size,
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const void *pValues)
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const void *pValues)
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{
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{
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TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
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memcpy((void*) cmd_buffer->push_constants + offset, pValues, size);
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}
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}
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VkResult
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VkResult
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@ -2255,7 +2257,8 @@ tu6_stage2shadersb(gl_shader_stage type)
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static void
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static void
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tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
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tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
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struct tu_descriptor_state *descriptors_state,
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struct tu_descriptor_state *descriptors_state,
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gl_shader_stage type)
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gl_shader_stage type,
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uint32_t *push_constants)
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{
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{
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const struct tu_program_descriptor_linkage *link =
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const struct tu_program_descriptor_linkage *link =
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&pipeline->program.link[type];
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&pipeline->program.link[type];
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@ -2263,7 +2266,6 @@ tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
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for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
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for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
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if (state->range[i].start < state->range[i].end) {
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if (state->range[i].start < state->range[i].end) {
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assert(i && i - 1 < link->ubo_map.num);
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uint32_t *ptr = map_get(descriptors_state, &link->ubo_map, i - 1);
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uint32_t *ptr = map_get(descriptors_state, &link->ubo_map, i - 1);
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uint32_t size = state->range[i].end - state->range[i].start;
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uint32_t size = state->range[i].end - state->range[i].start;
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@ -2282,6 +2284,21 @@ tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
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debug_assert((size % 16) == 0);
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debug_assert((size % 16) == 0);
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debug_assert((offset % 16) == 0);
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debug_assert((offset % 16) == 0);
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if (i == 0) {
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/* push constants */
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tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + (size / 4));
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tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
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CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
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CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
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CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
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CP_LOAD_STATE6_0_NUM_UNIT(size / 16));
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tu_cs_emit(cs, 0);
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tu_cs_emit(cs, 0);
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for (unsigned i = 0; i < size / 4; i++)
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tu_cs_emit(cs, push_constants[i + offset / 4]);
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continue;
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}
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tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
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tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
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tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
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tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(state->range[i].offset / 16) |
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CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
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CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
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@ -2329,18 +2346,18 @@ tu6_emit_ubos(struct tu_cs *cs, const struct tu_pipeline *pipeline,
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}
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}
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static struct tu_cs_entry
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static struct tu_cs_entry
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tu6_emit_consts(struct tu_device *device, struct tu_cs *draw_state,
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tu6_emit_consts(struct tu_cmd_buffer *cmd,
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const struct tu_pipeline *pipeline,
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const struct tu_pipeline *pipeline,
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struct tu_descriptor_state *descriptors_state,
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struct tu_descriptor_state *descriptors_state,
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gl_shader_stage type)
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gl_shader_stage type)
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{
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{
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struct tu_cs cs;
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struct tu_cs cs;
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tu_cs_begin_sub_stream(device, draw_state, 512, &cs); /* TODO: maximum size? */
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tu_cs_begin_sub_stream(cmd->device, &cmd->draw_state, 512, &cs); /* TODO: maximum size? */
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tu6_emit_user_consts(&cs, pipeline, descriptors_state, type);
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tu6_emit_user_consts(&cs, pipeline, descriptors_state, type, cmd->push_constants);
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tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
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tu6_emit_ubos(&cs, pipeline, descriptors_state, type);
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return tu_cs_end_sub_stream(draw_state, &cs);
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return tu_cs_end_sub_stream(&cmd->draw_state, &cs);
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}
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}
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static struct tu_cs_entry
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static struct tu_cs_entry
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@ -2603,15 +2620,13 @@ tu6_bind_draw_states(struct tu_cmd_buffer *cmd,
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(struct tu_draw_state_group) {
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(struct tu_draw_state_group) {
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.id = TU_DRAW_STATE_VS_CONST,
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.id = TU_DRAW_STATE_VS_CONST,
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.enable_mask = 0x7,
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.enable_mask = 0x7,
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.ib = tu6_emit_consts(cmd->device, &cmd->draw_state, pipeline,
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.ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_VERTEX)
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descriptors_state, MESA_SHADER_VERTEX)
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};
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};
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draw_state_groups[draw_state_group_count++] =
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draw_state_groups[draw_state_group_count++] =
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(struct tu_draw_state_group) {
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(struct tu_draw_state_group) {
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.id = TU_DRAW_STATE_FS_CONST,
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.id = TU_DRAW_STATE_FS_CONST,
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.enable_mask = 0x6,
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.enable_mask = 0x6,
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.ib = tu6_emit_consts(cmd->device, &cmd->draw_state, pipeline,
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.ib = tu6_emit_consts(cmd, pipeline, descriptors_state, MESA_SHADER_FRAGMENT)
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descriptors_state, MESA_SHADER_FRAGMENT)
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};
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};
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draw_state_groups[draw_state_group_count++] =
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draw_state_groups[draw_state_group_count++] =
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(struct tu_draw_state_group) {
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(struct tu_draw_state_group) {
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@ -922,7 +922,7 @@ struct tu_cmd_buffer
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struct tu_vertex_binding vertex_bindings[MAX_VBS];
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struct tu_vertex_binding vertex_bindings[MAX_VBS];
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uint32_t queue_family_index;
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uint32_t queue_family_index;
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uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
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uint32_t push_constants[MAX_PUSH_CONSTANTS_SIZE / 4];
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VkShaderStageFlags push_constant_stages;
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VkShaderStageFlags push_constant_stages;
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struct tu_descriptor_set meta_push_descriptors;
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struct tu_descriptor_set meta_push_descriptors;
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@ -225,6 +225,26 @@ static bool
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lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
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lower_intrinsic(nir_builder *b, nir_intrinsic_instr *instr,
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struct tu_shader *shader)
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struct tu_shader *shader)
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{
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{
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if (instr->intrinsic == nir_intrinsic_load_push_constant) {
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/* note: ir3 wants load_ubo, not load_uniform */
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assert(nir_intrinsic_base(instr) == 0);
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nir_intrinsic_instr *load =
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nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_ubo);
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load->num_components = instr->num_components;
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load->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
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load->src[1] = instr->src[0];
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nir_ssa_dest_init(&load->instr, &load->dest,
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load->num_components, instr->dest.ssa.bit_size,
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instr->dest.ssa.name);
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nir_builder_instr_insert(b, &load->instr);
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nir_ssa_def_rewrite_uses(&instr->dest.ssa, nir_src_for_ssa(&load->dest.ssa));
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nir_instr_remove(&instr->instr);
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return true;
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}
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if (instr->intrinsic != nir_intrinsic_vulkan_resource_index)
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if (instr->intrinsic != nir_intrinsic_vulkan_resource_index)
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return false;
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return false;
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@ -261,6 +281,7 @@ lower_impl(nir_function_impl *impl, struct tu_shader *shader)
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nir_foreach_block(block, impl) {
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nir_foreach_block(block, impl) {
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nir_foreach_instr_safe(instr, block) {
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nir_foreach_instr_safe(instr, block) {
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b.cursor = nir_before_instr(instr);
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switch (instr->type) {
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switch (instr->type) {
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case nir_instr_type_tex:
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case nir_instr_type_tex:
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progress |= lower_sampler(&b, nir_instr_as_tex(instr), shader);
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progress |= lower_sampler(&b, nir_instr_as_tex(instr), shader);
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@ -402,6 +423,9 @@ tu_shader_create(struct tu_device *dev,
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nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
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nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
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/* num_uniforms only used by ir3 for size of ubo 0 (push constants) */
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nir->num_uniforms = MAX_PUSH_CONSTANTS_SIZE / 16;
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shader->ir3_shader.compiler = dev->compiler;
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shader->ir3_shader.compiler = dev->compiler;
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shader->ir3_shader.type = stage;
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shader->ir3_shader.type = stage;
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shader->ir3_shader.nir = nir;
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shader->ir3_shader.nir = nir;
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