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turnip: depth/stencil 

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
This commit is contained in:
Jonathan Marek 2019-10-14 11:28:31 -04:00
parent f1efc9a1c8
commit 5b7fbcbdde
3 changed files with 95 additions and 20 deletions
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93
src/freedreno/vulkan/tu_cmd_buffer.c
View File

@ -391,7 +391,9 @@ tu6_emit_wfi(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
static void
tu6_emit_zs(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
const struct tu_framebuffer *fb = cmd->state.framebuffer;
const struct tu_subpass *subpass = cmd->state.subpass;
const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
const uint32_t a = subpass->depth_stencil_attachment.attachment;
if (a == VK_ATTACHMENT_UNUSED) {
@ -420,6 +422,40 @@ tu6_emit_zs(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
return;
}
uint32_t gmem_index = 0;
for (uint32_t i = 0; i < subpass->color_count; ++i) {
uint32_t a = subpass->color_attachments[i].attachment;
if (a != VK_ATTACHMENT_UNUSED)
gmem_index++;
}
const struct tu_image_view *iview = fb->attachments[a].attachment;
const struct tu_image_level *slice = &iview->image->levels[iview->base_mip];
enum a6xx_depth_format fmt = tu6_pipe2depth(iview->vk_format);
uint32_t offset = slice->offset + slice->size * iview->base_layer;
uint32_t stride = slice->pitch * iview->image->cpp;
tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_PITCH(stride));
tu_cs_emit(cs, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(slice->size));
tu_cs_emit_qw(cs, iview->image->bo->iova + iview->image->bo_offset + offset);
tu_cs_emit(cs, tiling->gmem_offsets[gmem_index]);
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
tu_cs_emit(cs, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
tu_cs_emit(cs, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 1);
tu_cs_emit(cs, 0x00000000); /* RB_STENCIL_INFO */
/* enable zs? */
}
@ -749,38 +785,47 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
}
static void
tu6_emit_tile_load(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu6_emit_tile_load_attachment(struct tu_cmd_buffer *cmd,
struct tu_cs *cs,
uint32_t a,
uint32_t gmem_index)
{
const struct tu_framebuffer *fb = cmd->state.framebuffer;
const struct tu_subpass *subpass = cmd->state.subpass;
const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
const struct tu_attachment_state *attachments = cmd->state.attachments;
const struct tu_image_view *iview = fb->attachments[a].attachment;
const struct tu_attachment_state *att = attachments + a;
if (att->pending_clear_aspects) {
tu6_emit_blit_clear(cmd, cs, iview,
tiling->gmem_offsets[gmem_index],
&att->clear_value);
} else {
tu6_emit_blit_info(cmd, cs, iview,
tiling->gmem_offsets[gmem_index],
A6XX_RB_BLIT_INFO_UNK0 | A6XX_RB_BLIT_INFO_GMEM);
}
tu6_emit_blit(cmd, cs);
}
static void
tu6_emit_tile_load(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
const struct tu_subpass *subpass = cmd->state.subpass;
tu6_emit_blit_scissor(cmd, cs);
uint32_t gmem_index = 0;
for (uint32_t i = 0; i < subpass->color_count; ++i) {
const uint32_t a = subpass->color_attachments[i].attachment;
if (a == VK_ATTACHMENT_UNUSED)
continue;
const struct tu_image_view *iview = fb->attachments[a].attachment;
const struct tu_attachment_state *att = attachments + a;
if (att->pending_clear_aspects) {
assert(att->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
tu6_emit_blit_clear(cmd, cs, iview,
tiling->gmem_offsets[gmem_index++],
&att->clear_value);
} else {
tu6_emit_blit_info(cmd, cs, iview,
tiling->gmem_offsets[gmem_index++],
A6XX_RB_BLIT_INFO_UNK0 | A6XX_RB_BLIT_INFO_GMEM);
}
tu6_emit_blit(cmd, cs);
if (a != VK_ATTACHMENT_UNUSED)
tu6_emit_tile_load_attachment(cmd, cs, a, gmem_index++);
}
/* load/clear zs? */
const uint32_t a = subpass->depth_stencil_attachment.attachment;
if (a != VK_ATTACHMENT_UNUSED)
tu6_emit_tile_load_attachment(cmd, cs, a, gmem_index);
}
static void
@ -821,6 +866,14 @@ tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
0);
tu6_emit_blit(cmd, cs);
}
const uint32_t a = cmd->state.subpass->depth_stencil_attachment.attachment;
if (a != VK_ATTACHMENT_UNUSED) {
const struct tu_image_view *iview = fb->attachments[a].attachment;
tu6_emit_blit_info(cmd, cs, iview, tiling->gmem_offsets[gmem_index],
0);
tu6_emit_blit(cmd, cs);
}
}
static void

21
src/freedreno/vulkan/tu_formats.c
View File

@ -394,6 +394,22 @@ tu6_rb_fmt_to_ifmt(enum a6xx_color_fmt fmt)
}
}
enum a6xx_depth_format
tu6_pipe2depth(VkFormat format)
{
switch (format) {
case VK_FORMAT_D16_UNORM:
return DEPTH6_16;
case VK_FORMAT_X8_D24_UNORM_PACK32:
case VK_FORMAT_D24_UNORM_S8_UINT:
return DEPTH6_24_8;
case VK_FORMAT_D32_SFLOAT:
return DEPTH6_32;
default:
return ~0;
}
}
static uint32_t
tu_pack_mask(int bits)
{
@ -649,6 +665,11 @@ tu_physical_device_get_format_properties(
tiled |= VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT | VK_FORMAT_FEATURE_BLIT_SRC_BIT | VK_FORMAT_FEATURE_BLIT_DST_BIT;
}
if (tu6_pipe2depth(format) != (enum a6xx_depth_format)~0) {
linear |= VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT;
tiled |= VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT;
}
end:
out_properties->linearTilingFeatures = linear;
out_properties->optimalTilingFeatures = tiled;

1
src/freedreno/vulkan/tu_private.h
View File

@ -1228,6 +1228,7 @@ tu_pack_clear_value(const VkClearValue *val,
VkFormat format,
uint32_t buf[4]);
enum a6xx_2d_ifmt tu6_rb_fmt_to_ifmt(enum a6xx_color_fmt fmt);
enum a6xx_depth_format tu6_pipe2depth(VkFormat format);
struct tu_image_level
{