radv: add support for cmd predication.
This doesn't get used yet, it just adds support to various PKT3 emissions to enable it later. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
880f21f55d
commit
a6c2001ace
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@ -1159,7 +1159,7 @@ radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
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uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
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uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
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cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
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cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
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radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
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radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
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COPY_DATA_DST_SEL(COPY_DATA_REG) |
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COPY_DATA_DST_SEL(COPY_DATA_REG) |
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COPY_DATA_COUNT_SEL);
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COPY_DATA_COUNT_SEL);
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@ -1168,7 +1168,7 @@ radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
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radeon_emit(cmd_buffer->cs, reg >> 2);
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radeon_emit(cmd_buffer->cs, reg >> 2);
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radeon_emit(cmd_buffer->cs, 0);
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radeon_emit(cmd_buffer->cs, 0);
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
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radeon_emit(cmd_buffer->cs, 0);
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radeon_emit(cmd_buffer->cs, 0);
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}
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}
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@ -2639,10 +2639,10 @@ void radv_CmdDraw(
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if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
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if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
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radeon_emit(cmd_buffer->cs, 0);
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radeon_emit(cmd_buffer->cs, 0);
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating));
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radeon_emit(cmd_buffer->cs, instanceCount);
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radeon_emit(cmd_buffer->cs, instanceCount);
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0));
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
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radeon_emit(cmd_buffer->cs, vertexCount);
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radeon_emit(cmd_buffer->cs, vertexCount);
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radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
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radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
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S_0287F0_USE_OPAQUE(0));
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S_0287F0_USE_OPAQUE(0));
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@ -3294,6 +3294,7 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
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* the stage mask. */
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* the stage mask. */
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si_cs_emit_write_event_eop(cs,
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si_cs_emit_write_event_eop(cs,
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cmd_buffer->state.predicating,
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cmd_buffer->device->physical_device->rad_info.chip_class,
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cmd_buffer->device->physical_device->rad_info.chip_class,
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false,
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false,
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EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
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EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
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@ -3345,7 +3346,7 @@ void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
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MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
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MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
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si_emit_wait_fence(cs, va, 1, 0xffffffff);
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si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
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assert(cmd_buffer->cs->cdw <= cdw_max);
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assert(cmd_buffer->cs->cdw <= cdw_max);
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}
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}
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@ -1095,6 +1095,7 @@ VkResult radv_CreateDevice(
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case RADV_QUEUE_GENERAL:
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case RADV_QUEUE_GENERAL:
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case RADV_QUEUE_COMPUTE:
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case RADV_QUEUE_COMPUTE:
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si_cs_emit_cache_flush(device->flush_cs[family],
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si_cs_emit_cache_flush(device->flush_cs[family],
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false,
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device->physical_device->rad_info.chip_class,
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device->physical_device->rad_info.chip_class,
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NULL, 0,
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NULL, 0,
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family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
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family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
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@ -1111,6 +1112,7 @@ VkResult radv_CreateDevice(
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case RADV_QUEUE_GENERAL:
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case RADV_QUEUE_GENERAL:
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case RADV_QUEUE_COMPUTE:
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case RADV_QUEUE_COMPUTE:
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si_cs_emit_cache_flush(device->flush_shader_cs[family],
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si_cs_emit_cache_flush(device->flush_shader_cs[family],
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false,
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device->physical_device->rad_info.chip_class,
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device->physical_device->rad_info.chip_class,
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NULL, 0,
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NULL, 0,
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family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
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family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
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@ -1761,6 +1763,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
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if (!i) {
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if (!i) {
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si_cs_emit_cache_flush(cs,
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si_cs_emit_cache_flush(cs,
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false,
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queue->device->physical_device->rad_info.chip_class,
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queue->device->physical_device->rad_info.chip_class,
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NULL, 0,
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NULL, 0,
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queue->queue_family_index == RING_COMPUTE &&
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queue->queue_family_index == RING_COMPUTE &&
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@ -776,6 +776,7 @@ struct radv_cmd_state {
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uint32_t descriptors_dirty;
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uint32_t descriptors_dirty;
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uint32_t trace_id;
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uint32_t trace_id;
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uint32_t last_ia_multi_vgt_param;
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uint32_t last_ia_multi_vgt_param;
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bool predicating;
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};
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};
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struct radv_cmd_pool {
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struct radv_cmd_pool {
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@ -848,6 +849,7 @@ uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
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bool instanced_draw, bool indirect_draw,
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bool instanced_draw, bool indirect_draw,
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uint32_t draw_vertex_count);
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uint32_t draw_vertex_count);
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void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
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void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
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bool predicated,
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enum chip_class chip_class,
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enum chip_class chip_class,
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bool is_mec,
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bool is_mec,
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unsigned event, unsigned event_flags,
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unsigned event, unsigned event_flags,
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@ -857,14 +859,17 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
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uint32_t new_fence);
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uint32_t new_fence);
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void si_emit_wait_fence(struct radeon_winsys_cs *cs,
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void si_emit_wait_fence(struct radeon_winsys_cs *cs,
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bool predicated,
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uint64_t va, uint32_t ref,
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uint64_t va, uint32_t ref,
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uint32_t mask);
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uint32_t mask);
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void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
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void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
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bool predicated,
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enum chip_class chip_class,
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enum chip_class chip_class,
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uint32_t *fence_ptr, uint64_t va,
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uint32_t *fence_ptr, uint64_t va,
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bool is_mec,
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bool is_mec,
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enum radv_cmd_flush_bits flush_bits);
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enum radv_cmd_flush_bits flush_bits);
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void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
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void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
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void si_emit_set_pred(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
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void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
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void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
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uint64_t src_va, uint64_t dest_va,
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uint64_t src_va, uint64_t dest_va,
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uint64_t size);
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uint64_t size);
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@ -992,7 +992,7 @@ void radv_CmdCopyQueryPoolResults(
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uint64_t avail_va = va + pool->availability_offset + 4 * query;
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uint64_t avail_va = va + pool->availability_offset + 4 * query;
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/* This waits on the ME. All copies below are done on the ME */
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/* This waits on the ME. All copies below are done on the ME */
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si_emit_wait_fence(cs, avail_va, 1, 0xffffffff);
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si_emit_wait_fence(cs, false, avail_va, 1, 0xffffffff);
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}
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}
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}
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}
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radv_query_shader(cmd_buffer, cmd_buffer->device->meta_state.query.pipeline_statistics_query_pipeline,
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radv_query_shader(cmd_buffer, cmd_buffer->device->meta_state.query.pipeline_statistics_query_pipeline,
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@ -1015,7 +1015,7 @@ void radv_CmdCopyQueryPoolResults(
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uint64_t avail_va = va + pool->availability_offset + 4 * query;
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uint64_t avail_va = va + pool->availability_offset + 4 * query;
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/* This waits on the ME. All copies below are done on the ME */
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/* This waits on the ME. All copies below are done on the ME */
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si_emit_wait_fence(cs, avail_va, 1, 0xffffffff);
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si_emit_wait_fence(cs, false, avail_va, 1, 0xffffffff);
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}
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}
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if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
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if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
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uint64_t avail_va = va + pool->availability_offset + 4 * query;
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uint64_t avail_va = va + pool->availability_offset + 4 * query;
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@ -1149,6 +1149,7 @@ void radv_CmdEndQuery(
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radeon_emit(cs, va >> 32);
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radeon_emit(cs, va >> 32);
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si_cs_emit_write_event_eop(cs,
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si_cs_emit_write_event_eop(cs,
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false,
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cmd_buffer->device->physical_device->rad_info.chip_class,
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cmd_buffer->device->physical_device->rad_info.chip_class,
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false,
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false,
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EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
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EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
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@ -1198,11 +1199,13 @@ void radv_CmdWriteTimestamp(
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break;
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break;
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default:
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default:
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si_cs_emit_write_event_eop(cs,
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si_cs_emit_write_event_eop(cs,
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false,
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cmd_buffer->device->physical_device->rad_info.chip_class,
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cmd_buffer->device->physical_device->rad_info.chip_class,
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mec,
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mec,
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V_028A90_BOTTOM_OF_PIPE_TS, 0,
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V_028A90_BOTTOM_OF_PIPE_TS, 0,
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3, query_va, 0, 0);
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3, query_va, 0, 0);
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si_cs_emit_write_event_eop(cs,
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si_cs_emit_write_event_eop(cs,
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false,
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cmd_buffer->device->physical_device->rad_info.chip_class,
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cmd_buffer->device->physical_device->rad_info.chip_class,
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mec,
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mec,
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V_028A90_BOTTOM_OF_PIPE_TS, 0,
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V_028A90_BOTTOM_OF_PIPE_TS, 0,
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@ -824,6 +824,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
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}
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}
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void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
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void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
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bool predicated,
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enum chip_class chip_class,
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enum chip_class chip_class,
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bool is_mec,
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bool is_mec,
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unsigned event, unsigned event_flags,
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unsigned event, unsigned event_flags,
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@ -838,7 +839,7 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
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unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
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unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
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if (chip_class >= GFX9 || is_gfx8_mec) {
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if (chip_class >= GFX9 || is_gfx8_mec) {
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radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, 0));
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radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, predicated));
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radeon_emit(cs, op);
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radeon_emit(cs, op);
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radeon_emit(cs, EOP_DATA_SEL(data_sel));
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radeon_emit(cs, EOP_DATA_SEL(data_sel));
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radeon_emit(cs, va); /* address lo */
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radeon_emit(cs, va); /* address lo */
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@ -854,7 +855,7 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
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* (and optional cache flushes executed) before the timestamp
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* (and optional cache flushes executed) before the timestamp
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* is written.
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* is written.
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*/
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*/
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
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radeon_emit(cs, op);
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radeon_emit(cs, op);
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radeon_emit(cs, va);
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radeon_emit(cs, va);
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radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
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radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
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@ -862,7 +863,7 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
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radeon_emit(cs, 0); /* unused */
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radeon_emit(cs, 0); /* unused */
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}
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}
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
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radeon_emit(cs, op);
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radeon_emit(cs, op);
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radeon_emit(cs, va);
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radeon_emit(cs, va);
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radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
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radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
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@ -873,10 +874,11 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
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void
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void
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si_emit_wait_fence(struct radeon_winsys_cs *cs,
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si_emit_wait_fence(struct radeon_winsys_cs *cs,
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bool predicated,
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uint64_t va, uint32_t ref,
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uint64_t va, uint32_t ref,
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uint32_t mask)
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uint32_t mask)
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{
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{
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radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
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radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, predicated));
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radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
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radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
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radeon_emit(cs, va);
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radeon_emit(cs, va);
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radeon_emit(cs, va >> 32);
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radeon_emit(cs, va >> 32);
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@ -887,12 +889,14 @@ si_emit_wait_fence(struct radeon_winsys_cs *cs,
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static void
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static void
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si_emit_acquire_mem(struct radeon_winsys_cs *cs,
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si_emit_acquire_mem(struct radeon_winsys_cs *cs,
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bool is_mec, bool is_gfx9,
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bool is_mec,
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bool predicated,
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bool is_gfx9,
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unsigned cp_coher_cntl)
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unsigned cp_coher_cntl)
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{
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{
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if (is_mec || is_gfx9) {
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if (is_mec || is_gfx9) {
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uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
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uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
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radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) |
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radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, predicated) |
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PKT3_SHADER_TYPE_S(is_mec));
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PKT3_SHADER_TYPE_S(is_mec));
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radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
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radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
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radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
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radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
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@ -902,7 +906,7 @@ si_emit_acquire_mem(struct radeon_winsys_cs *cs,
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radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
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radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
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} else {
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} else {
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/* ACQUIRE_MEM is only required on a compute ring. */
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/* ACQUIRE_MEM is only required on a compute ring. */
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radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
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radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, predicated));
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radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
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radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
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radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
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radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
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radeon_emit(cs, 0); /* CP_COHER_BASE */
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radeon_emit(cs, 0); /* CP_COHER_BASE */
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@ -912,6 +916,7 @@ si_emit_acquire_mem(struct radeon_winsys_cs *cs,
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void
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void
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si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
|
si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
|
||||||
|
bool predicated,
|
||||||
enum chip_class chip_class,
|
enum chip_class chip_class,
|
||||||
uint32_t *flush_cnt,
|
uint32_t *flush_cnt,
|
||||||
uint64_t flush_va,
|
uint64_t flush_va,
|
||||||
|
@ -942,6 +947,7 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
|
||||||
/* Necessary for DCC */
|
/* Necessary for DCC */
|
||||||
if (chip_class >= VI) {
|
if (chip_class >= VI) {
|
||||||
si_cs_emit_write_event_eop(cs,
|
si_cs_emit_write_event_eop(cs,
|
||||||
|
predicated,
|
||||||
chip_class,
|
chip_class,
|
||||||
is_mec,
|
is_mec,
|
||||||
V_028A90_FLUSH_AND_INV_CB_DATA_TS,
|
V_028A90_FLUSH_AND_INV_CB_DATA_TS,
|
||||||
|
@ -955,27 +961,27 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
|
||||||
}
|
}
|
||||||
|
|
||||||
if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
|
if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
|
||||||
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
|
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
|
||||||
radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
|
radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
|
||||||
}
|
}
|
||||||
|
|
||||||
if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
|
if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
|
||||||
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
|
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
|
||||||
radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
|
radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!flush_cb_db) {
|
if (!flush_cb_db) {
|
||||||
if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
|
if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
|
||||||
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
|
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
|
||||||
radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
|
radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
|
||||||
} else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
|
} else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
|
||||||
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
|
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
|
||||||
radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
|
radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
|
if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
|
||||||
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
|
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
|
||||||
radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
|
radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1022,14 +1028,14 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
|
||||||
assert(flush_cnt);
|
assert(flush_cnt);
|
||||||
uint32_t old_fence = (*flush_cnt)++;
|
uint32_t old_fence = (*flush_cnt)++;
|
||||||
|
|
||||||
si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags, 1,
|
si_cs_emit_write_event_eop(cs, predicated, chip_class, false, cb_db_event, tc_flags, 1,
|
||||||
flush_va, old_fence, *flush_cnt);
|
flush_va, old_fence, *flush_cnt);
|
||||||
si_emit_wait_fence(cs, flush_va, *flush_cnt, 0xffffffff);
|
si_emit_wait_fence(cs, predicated, flush_va, *flush_cnt, 0xffffffff);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* VGT state sync */
|
/* VGT state sync */
|
||||||
if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
|
if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
|
||||||
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
|
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
|
||||||
radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
|
radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1042,13 +1048,13 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
|
||||||
RADV_CMD_FLAG_INV_GLOBAL_L2 |
|
RADV_CMD_FLAG_INV_GLOBAL_L2 |
|
||||||
RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) &&
|
RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) &&
|
||||||
!is_mec) {
|
!is_mec) {
|
||||||
radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
|
radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, predicated));
|
||||||
radeon_emit(cs, 0);
|
radeon_emit(cs, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
|
if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
|
||||||
(chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
|
(chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
|
||||||
si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
|
si_emit_acquire_mem(cs, is_mec, predicated, chip_class >= GFX9,
|
||||||
cp_coher_cntl |
|
cp_coher_cntl |
|
||||||
S_0085F0_TC_ACTION_ENA(1) |
|
S_0085F0_TC_ACTION_ENA(1) |
|
||||||
S_0085F0_TCL1_ACTION_ENA(1) |
|
S_0085F0_TCL1_ACTION_ENA(1) |
|
||||||
|
@ -1062,14 +1068,16 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
|
||||||
*
|
*
|
||||||
* WB doesn't work without NC.
|
* WB doesn't work without NC.
|
||||||
*/
|
*/
|
||||||
si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
|
si_emit_acquire_mem(cs, is_mec, predicated,
|
||||||
|
chip_class >= GFX9,
|
||||||
cp_coher_cntl |
|
cp_coher_cntl |
|
||||||
S_0301F0_TC_WB_ACTION_ENA(1) |
|
S_0301F0_TC_WB_ACTION_ENA(1) |
|
||||||
S_0301F0_TC_NC_ACTION_ENA(1));
|
S_0301F0_TC_NC_ACTION_ENA(1));
|
||||||
cp_coher_cntl = 0;
|
cp_coher_cntl = 0;
|
||||||
}
|
}
|
||||||
if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) {
|
if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) {
|
||||||
si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
|
si_emit_acquire_mem(cs, is_mec,
|
||||||
|
predicated, chip_class >= GFX9,
|
||||||
cp_coher_cntl |
|
cp_coher_cntl |
|
||||||
S_0085F0_TCL1_ACTION_ENA(1));
|
S_0085F0_TCL1_ACTION_ENA(1));
|
||||||
cp_coher_cntl = 0;
|
cp_coher_cntl = 0;
|
||||||
|
@ -1080,7 +1088,7 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
|
||||||
* Therefore, it should be last. Done in PFP.
|
* Therefore, it should be last. Done in PFP.
|
||||||
*/
|
*/
|
||||||
if (cp_coher_cntl)
|
if (cp_coher_cntl)
|
||||||
si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, cp_coher_cntl);
|
si_emit_acquire_mem(cs, is_mec, predicated, chip_class >= GFX9, cp_coher_cntl);
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
@ -1110,6 +1118,7 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
|
||||||
ptr = &cmd_buffer->gfx9_fence_idx;
|
ptr = &cmd_buffer->gfx9_fence_idx;
|
||||||
}
|
}
|
||||||
si_cs_emit_cache_flush(cmd_buffer->cs,
|
si_cs_emit_cache_flush(cmd_buffer->cs,
|
||||||
|
cmd_buffer->state.predicating,
|
||||||
cmd_buffer->device->physical_device->rad_info.chip_class,
|
cmd_buffer->device->physical_device->rad_info.chip_class,
|
||||||
ptr, va,
|
ptr, va,
|
||||||
radv_cmd_buffer_uses_mec(cmd_buffer),
|
radv_cmd_buffer_uses_mec(cmd_buffer),
|
||||||
|
@ -1120,6 +1129,19 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
|
||||||
cmd_buffer->state.flush_bits = 0;
|
cmd_buffer->state.flush_bits = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
si_emit_set_pred(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
|
||||||
|
{
|
||||||
|
uint32_t val = 0;
|
||||||
|
|
||||||
|
if (va)
|
||||||
|
val = (((va >> 32) & 0xff) |
|
||||||
|
PRED_OP(PREDICATION_OP_BOOL64)|
|
||||||
|
PREDICATION_DRAW_VISIBLE);
|
||||||
|
radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
|
||||||
|
radeon_emit(cmd_buffer->cs, va);
|
||||||
|
radeon_emit(cmd_buffer->cs, val);
|
||||||
|
}
|
||||||
|
|
||||||
/* Set this if you want the 3D engine to wait until CP DMA is done.
|
/* Set this if you want the 3D engine to wait until CP DMA is done.
|
||||||
* It should be set on the last CP DMA packet. */
|
* It should be set on the last CP DMA packet. */
|
||||||
|
@ -1193,7 +1215,7 @@ static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
|
||||||
header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
|
header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
|
||||||
|
|
||||||
if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
|
if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
|
||||||
radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
|
radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
|
||||||
radeon_emit(cs, header);
|
radeon_emit(cs, header);
|
||||||
radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
|
radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
|
||||||
radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
|
radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
|
||||||
|
@ -1203,7 +1225,7 @@ static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
|
||||||
} else {
|
} else {
|
||||||
assert(!(flags & CP_DMA_USE_L2));
|
assert(!(flags & CP_DMA_USE_L2));
|
||||||
header |= S_411_SRC_ADDR_HI(src_va >> 32);
|
header |= S_411_SRC_ADDR_HI(src_va >> 32);
|
||||||
radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
|
radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
|
||||||
radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
|
radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
|
||||||
radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
|
radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
|
||||||
radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
|
radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
|
||||||
|
@ -1217,7 +1239,7 @@ static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
|
||||||
* should precede it.
|
* should precede it.
|
||||||
*/
|
*/
|
||||||
if ((flags & CP_DMA_SYNC) && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
|
if ((flags & CP_DMA_SYNC) && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
|
||||||
radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
|
radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
|
||||||
radeon_emit(cs, 0);
|
radeon_emit(cs, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue