diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 105384d315d..a2578126c52 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1159,7 +1159,7 @@ radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer, uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c; cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8); - radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0)); + radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating)); radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) | COPY_DATA_DST_SEL(COPY_DATA_REG) | COPY_DATA_COUNT_SEL); @@ -1168,7 +1168,7 @@ radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer, radeon_emit(cmd_buffer->cs, reg >> 2); radeon_emit(cmd_buffer->cs, 0); - radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); + radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating)); radeon_emit(cmd_buffer->cs, 0); } @@ -2639,10 +2639,10 @@ void radv_CmdDraw( if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3) radeon_emit(cmd_buffer->cs, 0); - radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0)); + radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, cmd_buffer->state.predicating)); radeon_emit(cmd_buffer->cs, instanceCount); - radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, 0)); + radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating)); radeon_emit(cmd_buffer->cs, vertexCount); radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX | S_0287F0_USE_OPAQUE(0)); @@ -3294,6 +3294,7 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer, * the stage mask. */ si_cs_emit_write_event_eop(cs, + cmd_buffer->state.predicating, cmd_buffer->device->physical_device->rad_info.chip_class, false, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, @@ -3345,7 +3346,7 @@ void radv_CmdWaitEvents(VkCommandBuffer commandBuffer, MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7); - si_emit_wait_fence(cs, va, 1, 0xffffffff); + si_emit_wait_fence(cs, false, va, 1, 0xffffffff); assert(cmd_buffer->cs->cdw <= cdw_max); } diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index f9328fb1677..8cf54427634 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -1095,6 +1095,7 @@ VkResult radv_CreateDevice( case RADV_QUEUE_GENERAL: case RADV_QUEUE_COMPUTE: si_cs_emit_cache_flush(device->flush_cs[family], + false, device->physical_device->rad_info.chip_class, NULL, 0, family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK, @@ -1111,6 +1112,7 @@ VkResult radv_CreateDevice( case RADV_QUEUE_GENERAL: case RADV_QUEUE_COMPUTE: si_cs_emit_cache_flush(device->flush_shader_cs[family], + false, device->physical_device->rad_info.chip_class, NULL, 0, family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK, @@ -1761,6 +1763,7 @@ radv_get_preamble_cs(struct radv_queue *queue, if (!i) { si_cs_emit_cache_flush(cs, + false, queue->device->physical_device->rad_info.chip_class, NULL, 0, queue->queue_family_index == RING_COMPUTE && diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index ac89fc1e8f2..a1674098845 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -776,6 +776,7 @@ struct radv_cmd_state { uint32_t descriptors_dirty; uint32_t trace_id; uint32_t last_ia_multi_vgt_param; + bool predicating; }; struct radv_cmd_pool { @@ -848,6 +849,7 @@ uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_draw, bool indirect_draw, uint32_t draw_vertex_count); void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs, + bool predicated, enum chip_class chip_class, bool is_mec, unsigned event, unsigned event_flags, @@ -857,14 +859,17 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs, uint32_t new_fence); void si_emit_wait_fence(struct radeon_winsys_cs *cs, + bool predicated, uint64_t va, uint32_t ref, uint32_t mask); void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, + bool predicated, enum chip_class chip_class, uint32_t *fence_ptr, uint64_t va, bool is_mec, enum radv_cmd_flush_bits flush_bits); void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer); +void si_emit_set_pred(struct radv_cmd_buffer *cmd_buffer, uint64_t va); void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, uint64_t dest_va, uint64_t size); diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index 03b5af16a55..3c40774042d 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -992,7 +992,7 @@ void radv_CmdCopyQueryPoolResults( uint64_t avail_va = va + pool->availability_offset + 4 * query; /* This waits on the ME. All copies below are done on the ME */ - si_emit_wait_fence(cs, avail_va, 1, 0xffffffff); + si_emit_wait_fence(cs, false, avail_va, 1, 0xffffffff); } } radv_query_shader(cmd_buffer, cmd_buffer->device->meta_state.query.pipeline_statistics_query_pipeline, @@ -1015,7 +1015,7 @@ void radv_CmdCopyQueryPoolResults( uint64_t avail_va = va + pool->availability_offset + 4 * query; /* This waits on the ME. All copies below are done on the ME */ - si_emit_wait_fence(cs, avail_va, 1, 0xffffffff); + si_emit_wait_fence(cs, false, avail_va, 1, 0xffffffff); } if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) { uint64_t avail_va = va + pool->availability_offset + 4 * query; @@ -1149,6 +1149,7 @@ void radv_CmdEndQuery( radeon_emit(cs, va >> 32); si_cs_emit_write_event_eop(cs, + false, cmd_buffer->device->physical_device->rad_info.chip_class, false, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, @@ -1198,11 +1199,13 @@ void radv_CmdWriteTimestamp( break; default: si_cs_emit_write_event_eop(cs, + false, cmd_buffer->device->physical_device->rad_info.chip_class, mec, V_028A90_BOTTOM_OF_PIPE_TS, 0, 3, query_va, 0, 0); si_cs_emit_write_event_eop(cs, + false, cmd_buffer->device->physical_device->rad_info.chip_class, mec, V_028A90_BOTTOM_OF_PIPE_TS, 0, diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index bf08214c551..ace9e665354 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -824,6 +824,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, } void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs, + bool predicated, enum chip_class chip_class, bool is_mec, unsigned event, unsigned event_flags, @@ -838,7 +839,7 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs, unsigned is_gfx8_mec = is_mec && chip_class < GFX9; if (chip_class >= GFX9 || is_gfx8_mec) { - radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, 0)); + radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, predicated)); radeon_emit(cs, op); radeon_emit(cs, EOP_DATA_SEL(data_sel)); radeon_emit(cs, va); /* address lo */ @@ -854,7 +855,7 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs, * (and optional cache flushes executed) before the timestamp * is written. */ - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0)); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated)); radeon_emit(cs, op); radeon_emit(cs, va); radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel)); @@ -862,7 +863,7 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs, radeon_emit(cs, 0); /* unused */ } - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0)); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated)); radeon_emit(cs, op); radeon_emit(cs, va); radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel)); @@ -873,10 +874,11 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs, void si_emit_wait_fence(struct radeon_winsys_cs *cs, + bool predicated, uint64_t va, uint32_t ref, uint32_t mask) { - radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); + radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, predicated)); radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1)); radeon_emit(cs, va); radeon_emit(cs, va >> 32); @@ -887,12 +889,14 @@ si_emit_wait_fence(struct radeon_winsys_cs *cs, static void si_emit_acquire_mem(struct radeon_winsys_cs *cs, - bool is_mec, bool is_gfx9, + bool is_mec, + bool predicated, + bool is_gfx9, unsigned cp_coher_cntl) { if (is_mec || is_gfx9) { uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff; - radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) | + radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, predicated) | PKT3_SHADER_TYPE_S(is_mec)); radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ @@ -902,7 +906,7 @@ si_emit_acquire_mem(struct radeon_winsys_cs *cs, radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ } else { /* ACQUIRE_MEM is only required on a compute ring. */ - radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0)); + radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, predicated)); radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ radeon_emit(cs, 0); /* CP_COHER_BASE */ @@ -912,6 +916,7 @@ si_emit_acquire_mem(struct radeon_winsys_cs *cs, void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, + bool predicated, enum chip_class chip_class, uint32_t *flush_cnt, uint64_t flush_va, @@ -942,6 +947,7 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, /* Necessary for DCC */ if (chip_class >= VI) { si_cs_emit_write_event_eop(cs, + predicated, chip_class, is_mec, V_028A90_FLUSH_AND_INV_CB_DATA_TS, @@ -955,27 +961,27 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, } if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated)); radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); } if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated)); radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); } if (!flush_cb_db) { if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated)); radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated)); radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); } } if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated)); radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4)); } @@ -1022,14 +1028,14 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, assert(flush_cnt); uint32_t old_fence = (*flush_cnt)++; - si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags, 1, + si_cs_emit_write_event_eop(cs, predicated, chip_class, false, cb_db_event, tc_flags, 1, flush_va, old_fence, *flush_cnt); - si_emit_wait_fence(cs, flush_va, *flush_cnt, 0xffffffff); + si_emit_wait_fence(cs, predicated, flush_va, *flush_cnt, 0xffffffff); } /* VGT state sync */ if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated)); radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); } @@ -1042,13 +1048,13 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, RADV_CMD_FLAG_INV_GLOBAL_L2 | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) && !is_mec) { - radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); + radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, predicated)); radeon_emit(cs, 0); } if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) || (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) { - si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, + si_emit_acquire_mem(cs, is_mec, predicated, chip_class >= GFX9, cp_coher_cntl | S_0085F0_TC_ACTION_ENA(1) | S_0085F0_TCL1_ACTION_ENA(1) | @@ -1062,14 +1068,16 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, * * WB doesn't work without NC. */ - si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, + si_emit_acquire_mem(cs, is_mec, predicated, + chip_class >= GFX9, cp_coher_cntl | S_0301F0_TC_WB_ACTION_ENA(1) | S_0301F0_TC_NC_ACTION_ENA(1)); cp_coher_cntl = 0; } if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) { - si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, + si_emit_acquire_mem(cs, is_mec, + predicated, chip_class >= GFX9, cp_coher_cntl | S_0085F0_TCL1_ACTION_ENA(1)); cp_coher_cntl = 0; @@ -1080,7 +1088,7 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, * Therefore, it should be last. Done in PFP. */ if (cp_coher_cntl) - si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, cp_coher_cntl); + si_emit_acquire_mem(cs, is_mec, predicated, chip_class >= GFX9, cp_coher_cntl); } void @@ -1110,6 +1118,7 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer) ptr = &cmd_buffer->gfx9_fence_idx; } si_cs_emit_cache_flush(cmd_buffer->cs, + cmd_buffer->state.predicating, cmd_buffer->device->physical_device->rad_info.chip_class, ptr, va, radv_cmd_buffer_uses_mec(cmd_buffer), @@ -1120,6 +1129,19 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer) cmd_buffer->state.flush_bits = 0; } +void +si_emit_set_pred(struct radv_cmd_buffer *cmd_buffer, uint64_t va) +{ + uint32_t val = 0; + + if (va) + val = (((va >> 32) & 0xff) | + PRED_OP(PREDICATION_OP_BOOL64)| + PREDICATION_DRAW_VISIBLE); + radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0)); + radeon_emit(cmd_buffer->cs, va); + radeon_emit(cmd_buffer->cs, val); +} /* Set this if you want the 3D engine to wait until CP DMA is done. * It should be set on the last CP DMA packet. */ @@ -1193,7 +1215,7 @@ static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer, header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2); if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) { - radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0)); + radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating)); radeon_emit(cs, header); radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */ radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */ @@ -1203,7 +1225,7 @@ static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer, } else { assert(!(flags & CP_DMA_USE_L2)); header |= S_411_SRC_ADDR_HI(src_va >> 32); - radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0)); + radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating)); radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */ radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */ radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */ @@ -1217,7 +1239,7 @@ static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer, * should precede it. */ if ((flags & CP_DMA_SYNC) && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) { - radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); + radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating)); radeon_emit(cs, 0); }