ac/gpu_info: remove unused has_unaligned_shader_loads
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
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@ -967,8 +967,6 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info)
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info->si_TA_CS_BC_BASE_ADDR_allowed = true;
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info->has_bo_metadata = true;
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info->has_eqaa_surface_allocator = info->gfx_level < GFX11;
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/* GFX6 doesn't support unaligned loads. */
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info->has_unaligned_shader_loads = info->gfx_level != GFX6;
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/* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
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* these faults are mitigated in software.
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*/
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@ -1570,7 +1568,6 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
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fprintf(f, " si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
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fprintf(f, " has_bo_metadata = %u\n", info->has_bo_metadata);
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fprintf(f, " has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
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fprintf(f, " has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
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fprintf(f, " has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
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fprintf(f, " has_stable_pstate = %u\n", info->has_stable_pstate);
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fprintf(f, " has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
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@ -186,7 +186,6 @@ struct radeon_info {
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bool si_TA_CS_BC_BASE_ADDR_allowed;
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bool has_bo_metadata;
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bool has_eqaa_surface_allocator;
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bool has_unaligned_shader_loads;
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bool has_sparse_vm_mappings;
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bool has_scheduled_fence_dependency;
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bool has_stable_pstate;
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@ -573,9 +573,6 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
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ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
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ws->info.has_bo_metadata = false;
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ws->info.has_eqaa_surface_allocator = false;
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/* GFX6 doesn't support unaligned loads. */
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ws->info.has_unaligned_shader_loads = ws->info.gfx_level == GFX7 &&
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ws->info.drm_minor >= 50;
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ws->info.has_sparse_vm_mappings = false;
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ws->info.max_alignment = 1024*1024;
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ws->info.has_graphics = true;
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