freedreno: Pull the tile_alignment lookup for a layout to a helper.
The r8g8 case UBWC alignment will be changing in the next commit, so fdl6_get_ubwc_blockwidth needs to start paying attention to r8g8 too. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4931>
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@ -35,7 +35,7 @@
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* missing UBWC blockwidth/blockheight for npot+64 cpp
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* missing 96/128 CPP for 8x MSAA with 32_32_32/32_32_32_32
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*/
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static const struct {
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static const struct tile_alignment {
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unsigned basealign;
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unsigned pitchalign;
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unsigned heightalign;
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@ -63,12 +63,23 @@ static const struct {
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#define RGB_TILE_HEIGHT_ALIGNMENT 16
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#define UBWC_PLANE_SIZE_ALIGNMENT 4096
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static const struct tile_alignment *
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fdl6_tile_alignment(struct fdl_layout *layout)
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{
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debug_assert(layout->cpp < ARRAY_SIZE(tile_alignment));
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if ((layout->cpp == 2) && (util_format_get_nr_components(layout->format) == 2))
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return &tile_alignment[0];
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else
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return &tile_alignment[layout->cpp];
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}
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static int
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fdl6_pitchalign(struct fdl_layout *layout, int ta, int level)
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fdl6_pitchalign(struct fdl_layout *layout, int level)
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{
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uint32_t pitchalign = 64;
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if (fdl_tile_mode(layout, level))
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pitchalign = tile_alignment[ta].pitchalign;
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pitchalign = fdl6_tile_alignment(layout)->pitchalign;
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return pitchalign;
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}
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@ -100,27 +111,22 @@ fdl6_layout(struct fdl_layout *layout,
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if (tile_alignment[layout->cpp].ubwc_blockwidth == 0)
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layout->ubwc = false;
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int ta = layout->cpp;
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/* The z16/r16 formats seem to not play by the normal tiling rules: */
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if ((layout->cpp == 2) && (util_format_get_nr_components(format) == 2))
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ta = 0;
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const struct tile_alignment *ta = fdl6_tile_alignment(layout);
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/* in layer_first layout, the level (slice) contains just one
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* layer (since in fact the layer contains the slices)
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*/
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uint32_t layers_in_level = layout->layer_first ? 1 : array_size;
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debug_assert(ta < ARRAY_SIZE(tile_alignment));
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debug_assert(tile_alignment[ta].pitchalign);
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debug_assert(ta->pitchalign);
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if (layout->tile_mode) {
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layout->base_align = tile_alignment[ta].basealign;
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layout->base_align = ta->basealign;
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} else {
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layout->base_align = 64;
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}
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uint32_t pitch0 = util_align_npot(width0, fdl6_pitchalign(layout, ta, 0));
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uint32_t pitch0 = util_align_npot(width0, fdl6_pitchalign(layout, 0));
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for (uint32_t level = 0; level < mip_levels; level++) {
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uint32_t depth = u_minify(depth0, level);
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@ -140,7 +146,7 @@ fdl6_layout(struct fdl_layout *layout,
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uint32_t nblocksy = util_format_get_nblocksy(format, height);
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if (tile_mode)
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nblocksy = align(nblocksy, tile_alignment[ta].heightalign);
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nblocksy = align(nblocksy, ta->heightalign);
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/* The blits used for mem<->gmem work at a granularity of
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* 32x32, which can cause faults due to over-fetch on the
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@ -154,7 +160,7 @@ fdl6_layout(struct fdl_layout *layout,
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uint32_t nblocksx =
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util_align_npot(util_format_get_nblocksx(format, u_minify(pitch0, level)),
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fdl6_pitchalign(layout, ta, level));
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fdl6_pitchalign(layout, level));
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slice->offset = layout->size;
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uint32_t blocks = nblocksx * nblocksy;
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@ -183,11 +189,9 @@ fdl6_layout(struct fdl_layout *layout,
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/* with UBWC every level is aligned to 4K */
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layout->size = align(layout->size, 4096);
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uint32_t block_width = tile_alignment[ta].ubwc_blockwidth;
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uint32_t block_height = tile_alignment[ta].ubwc_blockheight;
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uint32_t meta_pitch = align(DIV_ROUND_UP(width, block_width),
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uint32_t meta_pitch = align(DIV_ROUND_UP(width, ta->ubwc_blockwidth),
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RGB_TILE_WIDTH_ALIGNMENT);
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uint32_t meta_height = align(DIV_ROUND_UP(height, block_height),
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uint32_t meta_height = align(DIV_ROUND_UP(height, ta->ubwc_blockheight),
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RGB_TILE_HEIGHT_ALIGNMENT);
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/* it looks like mipmaps need alignment to power of two
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@ -227,6 +231,7 @@ void
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fdl6_get_ubwc_blockwidth(struct fdl_layout *layout,
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uint32_t *blockwidth, uint32_t *blockheight)
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{
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*blockwidth = tile_alignment[layout->cpp].ubwc_blockwidth;
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*blockheight = tile_alignment[layout->cpp].ubwc_blockheight;
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const struct tile_alignment *ta = fdl6_tile_alignment(layout);
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*blockwidth = ta->ubwc_blockwidth;
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*blockheight = ta->ubwc_blockheight;
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}
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