From 9cd60fce9c22737000a8f8dc711141f8a523fe75 Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Wed, 14 Jun 2017 14:48:11 -0700 Subject: [PATCH] i965/fs: Use align1 mode on ternary instructions on Gen10+ Align1 mode offers some nice features over align16, like access to more data types and the ability to use a 16-bit immediate. This patch does not start using any new features. It just emits ternary instructions in align1 mode. Reviewed-by: Scott D Phillips --- src/intel/compiler/brw_fs_generator.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 2622a919173..bdf2f916cba 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -1729,13 +1729,15 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) case BRW_OPCODE_MAD: assert(devinfo->gen >= 6); - brw_set_default_access_mode(p, BRW_ALIGN_16); + if (devinfo->gen < 10) + brw_set_default_access_mode(p, BRW_ALIGN_16); brw_MAD(p, dst, src[0], src[1], src[2]); break; case BRW_OPCODE_LRP: assert(devinfo->gen >= 6); - brw_set_default_access_mode(p, BRW_ALIGN_16); + if (devinfo->gen < 10) + brw_set_default_access_mode(p, BRW_ALIGN_16); brw_LRP(p, dst, src[0], src[1], src[2]); break; @@ -1833,7 +1835,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) case BRW_OPCODE_BFE: assert(devinfo->gen >= 7); - brw_set_default_access_mode(p, BRW_ALIGN_16); + if (devinfo->gen < 10) + brw_set_default_access_mode(p, BRW_ALIGN_16); brw_BFE(p, dst, src[0], src[1], src[2]); break; @@ -1843,7 +1846,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) break; case BRW_OPCODE_BFI2: assert(devinfo->gen >= 7); - brw_set_default_access_mode(p, BRW_ALIGN_16); + if (devinfo->gen < 10) + brw_set_default_access_mode(p, BRW_ALIGN_16); brw_BFI2(p, dst, src[0], src[1], src[2]); break;