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freedreno/drm: Use cached-coherent for control bo 

Userspace frequently reads the elapsed fence, but the GPU only writes it
once per submit.  So this should be another useful place for cached-
coherent.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11176>
This commit is contained in:
Rob Clark 2021-06-06 12:31:36 -07:00 committed by Marge Bot
parent f5879012ca
commit 926ffea994
1 changed files with 2 additions and 1 deletions
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3
src/freedreno/drm/freedreno_pipe.c
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@ -64,7 +64,8 @@ fd_pipe_new2(struct fd_device *dev, enum fd_pipe_id id, uint32_t prio)
pipe->dev_id.chip_id = val;
pipe->control_mem = fd_bo_new(dev, sizeof(*pipe->control),
0, "pipe-control");
FD_BO_CACHED_COHERENT,
"pipe-control");
pipe->control = fd_bo_map(pipe->control_mem);
/* We could be getting a bo from the bo-cache, make sure the fence value