From 926ffea994386af6511fa2ad4567d262692de179 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Sun, 6 Jun 2021 12:31:36 -0700 Subject: [PATCH] freedreno/drm: Use cached-coherent for control bo Userspace frequently reads the elapsed fence, but the GPU only writes it once per submit. So this should be another useful place for cached- coherent. Signed-off-by: Rob Clark Part-of: --- src/freedreno/drm/freedreno_pipe.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/freedreno/drm/freedreno_pipe.c b/src/freedreno/drm/freedreno_pipe.c index 53fd808821e..83052b98d11 100644 --- a/src/freedreno/drm/freedreno_pipe.c +++ b/src/freedreno/drm/freedreno_pipe.c @@ -64,7 +64,8 @@ fd_pipe_new2(struct fd_device *dev, enum fd_pipe_id id, uint32_t prio) pipe->dev_id.chip_id = val; pipe->control_mem = fd_bo_new(dev, sizeof(*pipe->control), - 0, "pipe-control"); + FD_BO_CACHED_COHERENT, + "pipe-control"); pipe->control = fd_bo_map(pipe->control_mem); /* We could be getting a bo from the bo-cache, make sure the fence value