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ac/surface: don't overwrite DCC settings for imported buffers 

Fixes: 0f6251b31f - ac/surface: use DCC compatible with image stores for < 4K resolutions

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13120>
This commit is contained in:
Marek Olšák 2021-09-30 09:50:47 -04:00
parent 5db5ff58b7
commit 923c535ee8
1 changed files with 14 additions and 9 deletions
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23
src/amd/common/ac_surface.c
View File

@ -2057,14 +2057,17 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
ac_modifier_fill_dcc_params(surf->modifier, surf, &AddrSurfInfoIn);
} else if (!AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.stencil) {
/* Optimal values for the L2 cache. */
if (info->chip_class == GFX9) {
surf->u.gfx9.color.dcc.independent_64B_blocks = 1;
surf->u.gfx9.color.dcc.independent_128B_blocks = 0;
surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
} else if (info->chip_class >= GFX10) {
surf->u.gfx9.color.dcc.independent_64B_blocks = 0;
surf->u.gfx9.color.dcc.independent_128B_blocks = 1;
surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
/* Don't change the DCC settings for imported buffers - they might differ. */
if (!(surf->flags & RADEON_SURF_IMPORTED)) {
if (info->chip_class == GFX9) {
surf->u.gfx9.color.dcc.independent_64B_blocks = 1;
surf->u.gfx9.color.dcc.independent_128B_blocks = 0;
surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
} else if (info->chip_class >= GFX10) {
surf->u.gfx9.color.dcc.independent_64B_blocks = 0;
surf->u.gfx9.color.dcc.independent_128B_blocks = 1;
surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
}
}
if (AddrSurfInfoIn.flags.display) {
@ -2081,7 +2084,9 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
}
/* Adjust DCC settings to meet DCN requirements. */
if (info->use_display_dcc_unaligned || info->use_display_dcc_with_retile_blit) {
/* Don't change the DCC settings for imported buffers - they might differ. */
if (!(surf->flags & RADEON_SURF_IMPORTED) &&
(info->use_display_dcc_unaligned || info->use_display_dcc_with_retile_blit)) {
/* Only Navi12/14 support independent 64B blocks in L2,
* but without DCC image stores.
*/