ac/llvm: handle write mask for nir_intrinsic_store_buffer_amd
tess lowering may generate buffer store with partial write mask. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
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@ -4241,10 +4241,19 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
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if (slc)
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if (slc)
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cache_policy |= ac_slc;
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cache_policy |= ac_slc;
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LLVMValueRef voffset = LLVMBuildAdd(ctx->ac.builder, addr_voffset,
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unsigned writemask = nir_intrinsic_write_mask(instr);
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LLVMConstInt(ctx->ac.i32, const_offset, 0), "");
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while (writemask) {
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ac_build_buffer_store_dword(&ctx->ac, descriptor, store_data, NULL, voffset, addr_soffset,
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int start, count;
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cache_policy);
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u_bit_scan_consecutive_range(&writemask, &start, &count);
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LLVMValueRef voffset = LLVMBuildAdd(
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ctx->ac.builder, addr_voffset,
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LLVMConstInt(ctx->ac.i32, const_offset + start * 4, 0), "");
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LLVMValueRef data = extract_vector_range(&ctx->ac, store_data, start, count);
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ac_build_buffer_store_dword(&ctx->ac, descriptor, data, NULL, voffset, addr_soffset,
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cache_policy);
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}
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break;
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break;
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}
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}
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case nir_intrinsic_has_input_vertex_amd: {
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case nir_intrinsic_has_input_vertex_amd: {
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