From 8f8d06bd059614c7b970549f02600e465d1f3d5b Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Wed, 25 May 2022 19:35:15 +0800 Subject: [PATCH] ac/llvm: handle write mask for nir_intrinsic_store_buffer_amd MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit tess lowering may generate buffer store with partial write mask. Reviewed-by: Marek Olšák Acked-by: Pierre-Eric Pelloux-Prayer Signed-off-by: Qiang Yu Part-of: --- src/amd/llvm/ac_nir_to_llvm.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 920fd5a0e19..7fc61f40936 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -4241,10 +4241,19 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins if (slc) cache_policy |= ac_slc; - LLVMValueRef voffset = LLVMBuildAdd(ctx->ac.builder, addr_voffset, - LLVMConstInt(ctx->ac.i32, const_offset, 0), ""); - ac_build_buffer_store_dword(&ctx->ac, descriptor, store_data, NULL, voffset, addr_soffset, - cache_policy); + unsigned writemask = nir_intrinsic_write_mask(instr); + while (writemask) { + int start, count; + u_bit_scan_consecutive_range(&writemask, &start, &count); + + LLVMValueRef voffset = LLVMBuildAdd( + ctx->ac.builder, addr_voffset, + LLVMConstInt(ctx->ac.i32, const_offset + start * 4, 0), ""); + + LLVMValueRef data = extract_vector_range(&ctx->ac, store_data, start, count); + ac_build_buffer_store_dword(&ctx->ac, descriptor, data, NULL, voffset, addr_soffset, + cache_policy); + } break; } case nir_intrinsic_has_input_vertex_amd: {