radeonsi: rename DCC_WRITE -> ALLOW_DCC_STORE
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
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@ -515,7 +515,7 @@ void si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, u
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if (is_dcc_decompress)
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image[1].access |= SI_IMAGE_ACCESS_DCC_OFF;
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else if (sctx->chip_class >= GFX10)
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image[1].access |= SI_IMAGE_ACCESS_DCC_WRITE;
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image[1].access |= SI_IMAGE_ACCESS_ALLOW_DCC_STORE;
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ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 2, 0, image);
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@ -815,7 +815,7 @@ void si_compute_clear_render_target(struct pipe_context *ctx, struct pipe_surfac
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struct pipe_image_view image = {0};
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image.resource = dstsurf->texture;
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image.shader_access = image.access = PIPE_IMAGE_ACCESS_WRITE | SI_IMAGE_ACCESS_DCC_WRITE;
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image.shader_access = image.access = PIPE_IMAGE_ACCESS_WRITE | SI_IMAGE_ACCESS_ALLOW_DCC_STORE;
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image.format = util_format_linear(dstsurf->format);
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image.u.tex.level = dstsurf->u.tex.level;
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image.u.tex.first_layer = 0; /* 3D images ignore first_layer (BASE_ARRAY) */
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@ -363,7 +363,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture
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/* DCC image stores require INDEPENDENT_128B_BLOCKS, which is not set
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* with displayable DCC on Navi12-14 due to DCN limitations. */
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S_00A018_WRITE_COMPRESS_ENABLE(tex->surface.u.gfx9.color.dcc.independent_128B_blocks &&
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access & SI_IMAGE_ACCESS_DCC_WRITE);
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access & SI_IMAGE_ACCESS_ALLOW_DCC_STORE);
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}
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state[7] = meta_va >> 16;
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@ -746,7 +746,7 @@ static void si_set_shader_image_desc(struct si_context *ctx, const struct pipe_i
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if (uses_dcc && !skip_decompress &&
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!(access & SI_IMAGE_ACCESS_DCC_OFF) &&
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((!(access & SI_IMAGE_ACCESS_DCC_WRITE) && (access & PIPE_IMAGE_ACCESS_WRITE)) ||
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((!(access & SI_IMAGE_ACCESS_ALLOW_DCC_STORE) && (access & PIPE_IMAGE_ACCESS_WRITE)) ||
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!vi_dcc_formats_compatible(screen, res->b.b.format, view->format))) {
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/* If DCC can't be disabled, at least decompress it.
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* The decompression is relatively cheap if the surface
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@ -170,8 +170,8 @@ enum si_clear_code
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DCC_UNCOMPRESSED = 0xFFFFFFFF,
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};
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#define SI_IMAGE_ACCESS_DCC_OFF (1 << 8)
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#define SI_IMAGE_ACCESS_DCC_WRITE (1 << 9)
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#define SI_IMAGE_ACCESS_DCC_OFF (1 << 8)
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#define SI_IMAGE_ACCESS_ALLOW_DCC_STORE (1 << 9)
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/* Debug flags. */
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enum
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