From 8c845d4cb47ef1ce5f0416eb25a87fea0be6b5e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 17 Aug 2021 18:58:20 -0400 Subject: [PATCH] radeonsi: rename DCC_WRITE -> ALLOW_DCC_STORE Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_compute_blit.c | 4 ++-- src/gallium/drivers/radeonsi/si_descriptors.c | 4 ++-- src/gallium/drivers/radeonsi/si_pipe.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c index bc229535645..97f747baebf 100644 --- a/src/gallium/drivers/radeonsi/si_compute_blit.c +++ b/src/gallium/drivers/radeonsi/si_compute_blit.c @@ -515,7 +515,7 @@ void si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, u if (is_dcc_decompress) image[1].access |= SI_IMAGE_ACCESS_DCC_OFF; else if (sctx->chip_class >= GFX10) - image[1].access |= SI_IMAGE_ACCESS_DCC_WRITE; + image[1].access |= SI_IMAGE_ACCESS_ALLOW_DCC_STORE; ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 2, 0, image); @@ -815,7 +815,7 @@ void si_compute_clear_render_target(struct pipe_context *ctx, struct pipe_surfac struct pipe_image_view image = {0}; image.resource = dstsurf->texture; - image.shader_access = image.access = PIPE_IMAGE_ACCESS_WRITE | SI_IMAGE_ACCESS_DCC_WRITE; + image.shader_access = image.access = PIPE_IMAGE_ACCESS_WRITE | SI_IMAGE_ACCESS_ALLOW_DCC_STORE; image.format = util_format_linear(dstsurf->format); image.u.tex.level = dstsurf->u.tex.level; image.u.tex.first_layer = 0; /* 3D images ignore first_layer (BASE_ARRAY) */ diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index e97d290186b..bfbc9b22d8c 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -363,7 +363,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture /* DCC image stores require INDEPENDENT_128B_BLOCKS, which is not set * with displayable DCC on Navi12-14 due to DCN limitations. */ S_00A018_WRITE_COMPRESS_ENABLE(tex->surface.u.gfx9.color.dcc.independent_128B_blocks && - access & SI_IMAGE_ACCESS_DCC_WRITE); + access & SI_IMAGE_ACCESS_ALLOW_DCC_STORE); } state[7] = meta_va >> 16; @@ -746,7 +746,7 @@ static void si_set_shader_image_desc(struct si_context *ctx, const struct pipe_i if (uses_dcc && !skip_decompress && !(access & SI_IMAGE_ACCESS_DCC_OFF) && - ((!(access & SI_IMAGE_ACCESS_DCC_WRITE) && (access & PIPE_IMAGE_ACCESS_WRITE)) || + ((!(access & SI_IMAGE_ACCESS_ALLOW_DCC_STORE) && (access & PIPE_IMAGE_ACCESS_WRITE)) || !vi_dcc_formats_compatible(screen, res->b.b.format, view->format))) { /* If DCC can't be disabled, at least decompress it. * The decompression is relatively cheap if the surface diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index d786859b4d4..ed89cac4f7b 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -170,8 +170,8 @@ enum si_clear_code DCC_UNCOMPRESSED = 0xFFFFFFFF, }; -#define SI_IMAGE_ACCESS_DCC_OFF (1 << 8) -#define SI_IMAGE_ACCESS_DCC_WRITE (1 << 9) +#define SI_IMAGE_ACCESS_DCC_OFF (1 << 8) +#define SI_IMAGE_ACCESS_ALLOW_DCC_STORE (1 << 9) /* Debug flags. */ enum