nir: Add upper bound for AMD shader arg intrinsics.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13155>
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@ -234,6 +234,9 @@ index("uint8_t", "offset1")
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# in hardware, instead of 4).
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index("bool", "st64")
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# When set, range analysis will use it for nir_unsigned_upper_bound
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index("unsigned", "arg_upper_bound_u32_amd")
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# Separate source/dest access flags for copies
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index("enum gl_access_qualifier", "dst_access")
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index("enum gl_access_qualifier", "src_access")
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@ -1346,8 +1349,8 @@ system_value("intersection_opaque_amd", 1, bit_sizes=[1])
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# Load forced VRS rates.
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intrinsic("load_force_vrs_rates_amd", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER])
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intrinsic("load_scalar_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER])
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intrinsic("load_vector_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER])
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intrinsic("load_scalar_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE, ARG_UPPER_BOUND_U32_AMD], flags=[CAN_ELIMINATE, CAN_REORDER])
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intrinsic("load_vector_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE, ARG_UPPER_BOUND_U32_AMD], flags=[CAN_ELIMINATE, CAN_REORDER])
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# src[] = { 64-bit base address, 32-bit offset }.
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intrinsic("load_smem_amd", src_comp=[1, 1], dest_comp=0, bit_sizes=[32],
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@ -1416,6 +1416,13 @@ nir_unsigned_upper_bound(nir_shader *shader, struct hash_table *range_ht,
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/* Very generous maximum: TCS/TES executed by largest possible workgroup */
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res = config->max_workgroup_invocations / MAX2(shader->info.tess.tcs_vertices_out, 1u);
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break;
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case nir_intrinsic_load_scalar_arg_amd:
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case nir_intrinsic_load_vector_arg_amd: {
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uint32_t upper_bound = nir_intrinsic_arg_upper_bound_u32_amd(intrin);
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if (upper_bound)
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res = upper_bound;
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break;
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}
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default:
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break;
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}
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