i965/vec4: Correct MUL destination hazard
As it turns out, we were over-thinking the cause of the hang on
Cherryview. It's simply errata for Cherryview.
commit 88fea85f09
Author: Ben Widawsky <benjamin.widawsky@intel.com>
Date: Fri Nov 21 10:47:41 2014 -0800
i965/vec4/gen8: Handle the MUL dest hazard exception
This is an explanation to why we never saw the hang on BDW.
NOTE: The problem the original patch was trying to fix does still exist. It will
have to be fixed at some point.
v2: Modify commit message, s/CHV/BDW
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84212
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
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@ -822,11 +822,11 @@ vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst)
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(reg.type == BRW_REGISTER_TYPE_UD || \
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reg.type == BRW_REGISTER_TYPE_D)
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/* From the destination hazard section of the spec:
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* > Instructions other than send, may use this control as long as operations
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* > that have different pipeline latencies are not mixed.
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/* "When source or destination datatype is 64b or operation is integer DWord
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* multiply, DepCtrl must not be used."
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* May apply to future SoCs as well.
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*/
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if (brw->gen >= 8) {
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if (brw->is_cherryview) {
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if (inst->opcode == BRW_OPCODE_MUL &&
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IS_DWORD(inst->src[0]) &&
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IS_DWORD(inst->src[1]))
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