vc4: Add a workaround for HW-2116 (state counter wrap fails).
I haven't proven that this happens (I've got other GPU hangs in the way), but the closed driver also does this and it's documented as an errata.
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@ -250,10 +250,10 @@ struct vc4_context {
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bool needs_flush;
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/**
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* Set when needs_flush, and the queued rendering is not just composed
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* of full-buffer clears.
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* Number of draw calls (not counting full buffer clears) queued in
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* the current job.
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*/
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bool draw_call_queued;
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uint32_t draw_calls_queued;
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/** Maximum index buffer valid for the current shader_rec. */
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uint32_t max_index;
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@ -100,7 +100,7 @@ vc4_start_draw(struct vc4_context *vc4)
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VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES));
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vc4->needs_flush = true;
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vc4->draw_call_queued = true;
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vc4->draw_calls_queued++;
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vc4->draw_width = width;
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vc4->draw_height = height;
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@ -226,6 +226,38 @@ vc4_emit_gl_shader_state(struct vc4_context *vc4, const struct pipe_draw_info *i
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vc4->max_index = max_index;
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}
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/**
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* HW-2116 workaround: Flush the batch before triggering the hardware state
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* counter wraparound behavior.
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*
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* State updates are tracked by a global counter which increments at the first
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* state update after a draw or a START_BINNING. Tiles can then have their
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* state updated at draw time with a set of cheap checks for whether the
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* state's copy of the global counter matches the global counter the last time
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* that state was written to the tile.
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*
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* The state counters are relatively small and wrap around quickly, so you
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* could get false negatives for needing to update a particular state in the
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* tile. To avoid this, the hardware attempts to write all of the state in
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* the tile at wraparound time. This apparently is broken, so we just flush
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* everything before that behavior is triggered. A batch flush is sufficient
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* to get our current contents drawn and reset the counters to 0.
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*
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* Note that we can't just use VC4_PACKET_FLUSH_ALL, because that caps the
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* tiles with VC4_PACKET_RETURN_FROM_LIST.
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*/
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static void
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vc4_hw_2116_workaround(struct pipe_context *pctx)
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{
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struct vc4_context *vc4 = vc4_context(pctx);
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if (vc4->draw_calls_queued == 0x1ef0) {
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perf_debug("Flushing batch due to HW-2116 workaround "
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"(too many draw calls per scene\n");
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vc4_flush(pctx);
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}
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}
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static void
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vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
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{
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@ -244,6 +276,8 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
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vc4_update_shadow_textures(pctx, &vc4->verttex);
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vc4_update_shadow_textures(pctx, &vc4->fragtex);
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vc4_hw_2116_workaround(pctx);
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vc4_get_draw_cl_space(vc4);
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if (vc4->prim_mode != info->mode) {
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@ -343,7 +377,7 @@ vc4_clear(struct pipe_context *pctx, unsigned buffers,
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/* We can't flag new buffers for clearing once we've queued draws. We
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* could avoid this by using the 3d engine to clear.
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*/
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if (vc4->draw_call_queued) {
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if (vc4->draw_calls_queued) {
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perf_debug("Flushing rendering to process new clear.\n");
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vc4_flush(pctx);
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}
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@ -55,7 +55,7 @@ vc4_job_reset(struct vc4_context *vc4)
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vc4->shader_rec_count = 0;
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vc4->needs_flush = false;
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vc4->draw_call_queued = false;
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vc4->draw_calls_queued = 0;
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/* We have no hardware context saved between our draw calls, so we
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* need to flag the next draw as needing all state emitted. Emitting
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