KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

freedreno: a2xx: enable early-Z testing 

Enable earlyZ when alpha test is disabled.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Jonathan Marek 2018-11-23 10:58:11 -05:00 committed by Rob Clark
parent 32b1d2d716
commit 7c930d99ad
4 changed files with 11 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/gallium/drivers/freedreno/a2xx/fd2_emit.c
View File

@ -190,6 +190,7 @@ fd2_emit_state(struct fd_context *ctx, const enum fd_dirty_3d_state dirty)
{
struct fd2_blend_stateobj *blend = fd2_blend_stateobj(ctx->blend);
struct fd2_zsa_stateobj *zsa = fd2_zsa_stateobj(ctx->zsa);
struct fd2_shader_stateobj *fp = ctx->prog.fp;
struct fd_ringbuffer *ring = ctx->batch->draw;
/* NOTE: we probably want to eventually refactor this so each state
@ -205,12 +206,16 @@ fd2_emit_state(struct fd_context *ctx, const enum fd_dirty_3d_state dirty)
OUT_RING(ring, ctx->sample_mask);
}
if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF | FD_DIRTY_PROG)) {
struct pipe_stencil_ref *sr = &ctx->stencil_ref;
uint32_t val = zsa->rb_depthcontrol;
if (fp->has_kill)
val &= ~A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE;
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
OUT_RING(ring, zsa->rb_depthcontrol);
OUT_RING(ring, val);
OUT_PKT3(ring, CP_SET_CONSTANT, 4);
OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF));

1
src/gallium/drivers/freedreno/a2xx/fd2_program.h
View File

@ -51,6 +51,7 @@ struct fd2_shader_stateobj {
bool writes_psize;
bool need_param;
bool has_kill;
/* note:
* fragment shader only has one variant

3
src/gallium/drivers/freedreno/a2xx/fd2_zsa.c
View File

@ -49,7 +49,8 @@ fd2_zsa_state_create(struct pipe_context *pctx,
A2XX_RB_DEPTHCONTROL_ZFUNC(cso->depth.func); /* maps 1:1 */
if (cso->depth.enabled)
so->rb_depthcontrol |= A2XX_RB_DEPTHCONTROL_Z_ENABLE;
so->rb_depthcontrol |= A2XX_RB_DEPTHCONTROL_Z_ENABLE |
COND(!cso->alpha.enabled, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
if (cso->depth.writemask)
so->rb_depthcontrol |= A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE;

1
src/gallium/drivers/freedreno/a2xx/ir2_nir.c
View File

@ -633,6 +633,7 @@ emit_intrinsic(struct ir2_context *ctx, nir_intrinsic_instr *intr)
}
instr->alu.export = -1;
instr->src_count = 1;
ctx->so->has_kill = true;
break;
case nir_intrinsic_load_front_face:
/* gl_FrontFacing is in the sign of param.x