pvr: Fix physical device limits.
This commit changes to the physical device limits which were missed during the 1.17 transition. Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com> Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17206>
This commit is contained in:
Karmjit Mahil
Marge Bot
parent
eac5a2fdfa
commit
7858c32550
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@ -46,6 +46,7 @@ const struct pvr_device_features pvr_device_features_4_V_2_51 = {
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.has_gs_rta_support = true,
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.has_isp_max_tiles_in_flight = true,
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.has_isp_samples_per_pixel = true,
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.has_max_instances_per_pds_task = true,
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.has_max_multisample = true,
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.has_max_partitions = true,
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.has_max_usc_tasks = true,
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@ -63,6 +64,7 @@ const struct pvr_device_features pvr_device_features_4_V_2_51 = {
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.has_tpu_image_state_v2 = true,
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.has_usc_f16sop_u8 = true,
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.has_usc_min_output_registers_per_pix = true,
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.has_usc_slots = true,
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.has_uvs_banks = true,
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.has_uvs_pba_entries = true,
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.has_uvs_vtx_entries = true,
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@ -73,6 +75,7 @@ const struct pvr_device_features pvr_device_features_4_V_2_51 = {
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.common_store_size_in_dwords = 1280U * 4U * 4U,
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.isp_max_tiles_in_flight = 4U,
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.isp_samples_per_pixel = 2U,
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.max_instances_per_pds_task = 32U,
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.max_multisample = 8U,
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.max_partitions = 8U,
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.max_usc_tasks = 56U,
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@ -83,6 +86,7 @@ const struct pvr_device_features pvr_device_features_4_V_2_51 = {
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.tile_size_x = 32U,
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.tile_size_y = 32U,
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.usc_min_output_registers_per_pix = 2U,
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.usc_slots = 32U,
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.uvs_banks = 8U,
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.uvs_pba_entries = 320U,
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.uvs_vtx_entries = 288U,
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@ -126,6 +130,7 @@ const struct pvr_device_features pvr_device_features_33_V_11_3 = {
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.has_compute = true,
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.has_isp_max_tiles_in_flight = true,
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.has_isp_samples_per_pixel = true,
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.has_max_instances_per_pds_task = true,
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.has_max_multisample = true,
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.has_max_partitions = true,
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.has_max_usc_tasks = true,
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@ -146,6 +151,7 @@ const struct pvr_device_features pvr_device_features_33_V_11_3 = {
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.has_usc_f16sop_u8 = true,
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.has_usc_min_output_registers_per_pix = true,
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.has_usc_pixel_partition_mask = true,
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.has_usc_slots = true,
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.has_uvs_banks = true,
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.has_uvs_pba_entries = true,
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.has_uvs_vtx_entries = true,
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@ -154,6 +160,7 @@ const struct pvr_device_features pvr_device_features_33_V_11_3 = {
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.common_store_size_in_dwords = 512U * 4U * 4U,
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.isp_max_tiles_in_flight = 1U,
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.isp_samples_per_pixel = 1U,
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.max_instances_per_pds_task = 32U,
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.max_multisample = 4U,
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.max_partitions = 4U,
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.max_usc_tasks = 24U,
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@ -165,6 +172,7 @@ const struct pvr_device_features pvr_device_features_33_V_11_3 = {
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.tile_size_x = 16U,
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.tile_size_y = 16U,
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.usc_min_output_registers_per_pix = 1U,
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.usc_slots = 14U,
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.uvs_banks = 2U,
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.uvs_pba_entries = 320U,
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.uvs_vtx_entries = 288U,
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@ -199,6 +207,7 @@ const struct pvr_device_features pvr_device_features_36_V_104_796 = {
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.has_gs_rta_support = true,
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.has_isp_max_tiles_in_flight = true,
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.has_isp_samples_per_pixel = true,
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.has_max_instances_per_pds_task = true,
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.has_max_multisample = true,
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.has_max_partitions = true,
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.has_max_usc_tasks = true,
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@ -221,6 +230,7 @@ const struct pvr_device_features pvr_device_features_36_V_104_796 = {
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.has_usc_f16sop_u8 = true,
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.has_usc_min_output_registers_per_pix = true,
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.has_usc_pixel_partition_mask = true,
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.has_usc_slots = true,
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.has_uvs_banks = true,
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.has_uvs_pba_entries = true,
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.has_uvs_vtx_entries = true,
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@ -230,6 +240,7 @@ const struct pvr_device_features pvr_device_features_36_V_104_796 = {
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.common_store_size_in_dwords = 1344U * 4U * 4U,
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.isp_max_tiles_in_flight = 6U,
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.isp_samples_per_pixel = 4U,
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.max_instances_per_pds_task = 32U,
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.max_multisample = 4U,
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.max_partitions = 16U,
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.max_usc_tasks = 156U,
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@ -241,6 +252,7 @@ const struct pvr_device_features pvr_device_features_36_V_104_796 = {
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.tile_size_x = 16U,
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.tile_size_y = 16U,
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.usc_min_output_registers_per_pix = 2U,
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.usc_slots = 64U,
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.uvs_banks = 8U,
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.uvs_pba_entries = 160U,
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.uvs_vtx_entries = 144U,
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@ -259,6 +259,7 @@ struct pvr_device_features {
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bool has_gs_rta_support : 1;
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bool has_isp_max_tiles_in_flight : 1;
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bool has_isp_samples_per_pixel : 1;
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bool has_max_instances_per_pds_task : 1;
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bool has_max_multisample : 1;
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bool has_max_partitions : 1;
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bool has_max_usc_tasks : 1;
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@ -285,6 +286,7 @@ struct pvr_device_features {
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bool has_usc_f16sop_u8 : 1;
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bool has_usc_min_output_registers_per_pix : 1;
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bool has_usc_pixel_partition_mask : 1;
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bool has_usc_slots : 1;
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bool has_uvs_banks : 1;
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bool has_uvs_pba_entries : 1;
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bool has_uvs_vtx_entries : 1;
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@ -296,6 +298,7 @@ struct pvr_device_features {
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uint32_t common_store_size_in_dwords;
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uint32_t isp_max_tiles_in_flight;
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uint32_t isp_samples_per_pixel;
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uint32_t max_instances_per_pds_task;
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uint32_t max_multisample;
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uint32_t max_partitions;
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uint32_t max_usc_tasks;
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@ -307,6 +310,7 @@ struct pvr_device_features {
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uint32_t tile_size_x;
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uint32_t tile_size_y;
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uint32_t usc_min_output_registers_per_pix;
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uint32_t usc_slots;
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uint32_t uvs_banks;
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uint32_t uvs_pba_entries;
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uint32_t uvs_vtx_entries;
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@ -819,6 +819,33 @@ void pvr_GetPhysicalDeviceProperties2(VkPhysicalDevice physicalDevice,
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const uint32_t max_user_vertex_components =
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((uvs_banks <= 8U) && (uvs_pba_entries == 160U)) ? 64U : 128U;
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/* The workgroup invocations are limited by the case where we have a compute
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* barrier - each slot has a fixed number of invocations, the whole workgroup
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* may need to span multiple slots. As each slot will WAIT at the barrier
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* until the last invocation completes, all have to be schedulable at the
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* same time.
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*
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* Typically all Rogue cores have 16 slots. Some of the smallest cores are
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* reduced to 14.
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*
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* The compute barrier slot exhaustion scenario can be tested with:
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* dEQP-VK.memory_model.message_passing*u32.coherent.fence_fence
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* .atomicwrite*guard*comp
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*/
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/* Default value based on the minimum value found in all existing cores. */
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const uint32_t usc_slots =
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PVR_GET_FEATURE_VALUE(&pdevice->dev_info, usc_slots, 14);
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/* Default value based on the minimum value found in all existing cores. */
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const uint32_t max_instances_per_pds_task =
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PVR_GET_FEATURE_VALUE(&pdevice->dev_info,
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max_instances_per_pds_task,
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32U);
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const uint32_t max_compute_work_group_invocations =
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(usc_slots * max_instances_per_pds_task >= 512U) ? 512U : 384U;
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VkPhysicalDeviceLimits limits = {
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.maxImageDimension1D = max_render_size,
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.maxImageDimension2D = max_render_size,
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@ -879,28 +906,33 @@ void pvr_GetPhysicalDeviceProperties2(VkPhysicalDevice physicalDevice,
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.maxTessellationEvaluationOutputComponents = 0,
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/* Geometry Shader Limits */
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.maxGeometryShaderInvocations = 32U,
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.maxGeometryInputComponents = max_user_vertex_components,
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.maxGeometryOutputComponents = max_user_vertex_components,
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.maxGeometryOutputVertices = 256U,
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.maxGeometryTotalOutputComponents = 1024U,
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.maxGeometryShaderInvocations = 0,
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.maxGeometryInputComponents = 0,
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.maxGeometryOutputComponents = 0,
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.maxGeometryOutputVertices = 0,
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.maxGeometryTotalOutputComponents = 0,
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/* Fragment Shader Limits */
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.maxFragmentInputComponents = max_user_vertex_components,
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.maxFragmentOutputAttachments = PVR_MAX_COLOR_ATTACHMENTS,
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.maxFragmentDualSrcAttachments = 0,
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.maxFragmentCombinedOutputResources = 8U,
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.maxFragmentCombinedOutputResources =
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descriptor_limits->max_per_stage_storage_buffers +
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descriptor_limits->max_per_stage_storage_images +
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PVR_MAX_COLOR_ATTACHMENTS,
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/* Compute Shader Limits */
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.maxComputeSharedMemorySize = 16U * 1024U,
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.maxComputeWorkGroupCount = { 64U * 1024U, 64U * 1024U, 64U * 1024U },
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.maxComputeWorkGroupInvocations = 512U,
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.maxComputeWorkGroupSize = { 512U, 512U, 64U },
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.maxComputeWorkGroupInvocations = max_compute_work_group_invocations,
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.maxComputeWorkGroupSize = { max_compute_work_group_invocations,
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max_compute_work_group_invocations,
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64U },
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/* Rasterization Limits */
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.subPixelPrecisionBits = sub_pixel_precision,
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.subTexelPrecisionBits = 8U,
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.mipmapPrecisionBits = 4U,
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.mipmapPrecisionBits = 8U,
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.maxDrawIndexedIndexValue = UINT32_MAX,
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.maxDrawIndirectCount = 2U * 1024U * 1024U * 1024U,
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@ -921,8 +953,8 @@ void pvr_GetPhysicalDeviceProperties2(VkPhysicalDevice physicalDevice,
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.minTexelOffset = -8,
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.maxTexelOffset = 7U,
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.minTexelGatherOffset = 0,
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.maxTexelGatherOffset = 0,
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.minTexelGatherOffset = -8,
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.maxTexelGatherOffset = 7,
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.minInterpolationOffset = -0.5,
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.maxInterpolationOffset = 0.5,
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.subPixelInterpolationOffsetBits = 4U,
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@ -32,12 +32,12 @@
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#include "pvr_device_info.h"
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#include "util/u_math.h"
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#define PVR_MAX_COLOR_ATTACHMENTS 8U
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#define PVR_MAX_COLOR_ATTACHMENTS 8U /* Number of PBE emit registers. */
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#define PVR_MAX_QUEUES 2U
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#define PVR_MAX_VIEWPORTS 1U
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#define PVR_MAX_NEG_OFFSCREEN_OFFSET 4096U
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#define PVR_MAX_PUSH_CONSTANTS_SIZE 128U
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#define PVR_MAX_PUSH_CONSTANTS_SIZE 256U
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#define PVR_MAX_DESCRIPTOR_SETS 4U
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#define PVR_MAX_FRAMEBUFFER_LAYERS ROGUE_MAX_RENDER_TARGETS
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