anv: make apply_pipeline_layout/compute_push_layout visible to NIR debug
Useful for debug. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17209>
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@ -70,15 +70,15 @@ anv_nir_ubo_addr_format(const struct anv_physical_device *pdevice,
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bool anv_nir_lower_ubo_loads(nir_shader *shader);
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void anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
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void anv_nir_apply_pipeline_layout(nir_shader *shader,
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const struct anv_physical_device *pdevice,
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bool robust_buffer_access,
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const struct anv_pipeline_layout *layout,
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nir_shader *shader,
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struct anv_pipeline_bind_map *map);
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void anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
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void anv_nir_compute_push_layout(nir_shader *nir,
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const struct anv_physical_device *pdevice,
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bool robust_buffer_access,
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nir_shader *nir,
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struct brw_stage_prog_data *prog_data,
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struct anv_pipeline_bind_map *map,
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void *mem_ctx);
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@ -1411,10 +1411,10 @@ compare_binding_infos(const void *_a, const void *_b)
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}
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void
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anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
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anv_nir_apply_pipeline_layout(nir_shader *shader,
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const struct anv_physical_device *pdevice,
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bool robust_buffer_access,
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const struct anv_pipeline_layout *layout,
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nir_shader *shader,
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struct anv_pipeline_bind_map *map)
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{
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void *mem_ctx = ralloc_context(NULL);
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@ -29,9 +29,9 @@
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#define sizeof_field(type, field) sizeof(((type *)0)->field)
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void
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anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
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anv_nir_compute_push_layout(nir_shader *nir,
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const struct anv_physical_device *pdevice,
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bool robust_buffer_access,
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nir_shader *nir,
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struct brw_stage_prog_data *prog_data,
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struct anv_pipeline_bind_map *map,
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void *mem_ctx)
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@ -788,9 +788,9 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
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NIR_PASS(_, nir, brw_nir_lower_ray_queries, &pdevice->info);
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/* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
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anv_nir_apply_pipeline_layout(pdevice,
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pipeline->device->robust_buffer_access,
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layout, nir, &stage->bind_map);
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NIR_PASS_V(nir, anv_nir_apply_pipeline_layout,
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pdevice, pipeline->device->robust_buffer_access,
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layout, &stage->bind_map);
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NIR_PASS(_, nir, nir_lower_explicit_io, nir_var_mem_ubo,
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anv_nir_ubo_addr_format(pdevice,
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@ -818,8 +818,9 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
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.callback = NULL,
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});
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anv_nir_compute_push_layout(pdevice, pipeline->device->robust_buffer_access,
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nir, prog_data, &stage->bind_map, mem_ctx);
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NIR_PASS_V(nir, anv_nir_compute_push_layout,
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pdevice, pipeline->device->robust_buffer_access,
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prog_data, &stage->bind_map, mem_ctx);
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if (gl_shader_stage_uses_workgroup(nir->info.stage)) {
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if (!nir->info.shared_memory_explicit_layout) {
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