anv: make apply_pipeline_layout/compute_push_layout visible to NIR debug

Useful for debug.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17209>
This commit is contained in:
Lionel Landwerlin 2022-06-23 15:26:17 +03:00 committed by Marge Bot
parent ed429af586
commit eac5a2fdfa
4 changed files with 14 additions and 13 deletions

View File

@ -70,15 +70,15 @@ anv_nir_ubo_addr_format(const struct anv_physical_device *pdevice,
bool anv_nir_lower_ubo_loads(nir_shader *shader);
void anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
void anv_nir_apply_pipeline_layout(nir_shader *shader,
const struct anv_physical_device *pdevice,
bool robust_buffer_access,
const struct anv_pipeline_layout *layout,
nir_shader *shader,
struct anv_pipeline_bind_map *map);
void anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
void anv_nir_compute_push_layout(nir_shader *nir,
const struct anv_physical_device *pdevice,
bool robust_buffer_access,
nir_shader *nir,
struct brw_stage_prog_data *prog_data,
struct anv_pipeline_bind_map *map,
void *mem_ctx);

View File

@ -1411,10 +1411,10 @@ compare_binding_infos(const void *_a, const void *_b)
}
void
anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
anv_nir_apply_pipeline_layout(nir_shader *shader,
const struct anv_physical_device *pdevice,
bool robust_buffer_access,
const struct anv_pipeline_layout *layout,
nir_shader *shader,
struct anv_pipeline_bind_map *map)
{
void *mem_ctx = ralloc_context(NULL);

View File

@ -29,9 +29,9 @@
#define sizeof_field(type, field) sizeof(((type *)0)->field)
void
anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
anv_nir_compute_push_layout(nir_shader *nir,
const struct anv_physical_device *pdevice,
bool robust_buffer_access,
nir_shader *nir,
struct brw_stage_prog_data *prog_data,
struct anv_pipeline_bind_map *map,
void *mem_ctx)

View File

@ -788,9 +788,9 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
NIR_PASS(_, nir, brw_nir_lower_ray_queries, &pdevice->info);
/* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
anv_nir_apply_pipeline_layout(pdevice,
pipeline->device->robust_buffer_access,
layout, nir, &stage->bind_map);
NIR_PASS_V(nir, anv_nir_apply_pipeline_layout,
pdevice, pipeline->device->robust_buffer_access,
layout, &stage->bind_map);
NIR_PASS(_, nir, nir_lower_explicit_io, nir_var_mem_ubo,
anv_nir_ubo_addr_format(pdevice,
@ -818,8 +818,9 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
.callback = NULL,
});
anv_nir_compute_push_layout(pdevice, pipeline->device->robust_buffer_access,
nir, prog_data, &stage->bind_map, mem_ctx);
NIR_PASS_V(nir, anv_nir_compute_push_layout,
pdevice, pipeline->device->robust_buffer_access,
prog_data, &stage->bind_map, mem_ctx);
if (gl_shader_stage_uses_workgroup(nir->info.stage)) {
if (!nir->info.shared_memory_explicit_layout) {