gallium/radeon: add RADEON_FLAG_HANDLE
When passed to winsys->buffer_create, this flag will indicate that we require a buffer that maps 1:1 with a kernel buffer handle. This is currently set for all textures, since textures can potentially be exported to other processes. This is not a huge loss, since the main purpose of this patch series is to deal with applications that allocate many small buffers. A hypothetical application with tons of tiny textures might still benefit from not setting this flag, but that's not a use case I'm worried about just now. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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@ -1114,7 +1114,7 @@ r300_texture_create_object(struct r300_screen *rscreen,
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/* Create the backing buffer if needed. */
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if (!tex->buf) {
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tex->buf = rws->buffer_create(rws, tex->tex.size_in_bytes, 2048,
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tex->domain, 0);
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tex->domain, RADEON_FLAG_HANDLE);
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if (!tex->buf) {
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goto fail;
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@ -1117,6 +1117,8 @@ r600_texture_create_object(struct pipe_screen *screen,
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r600_init_resource_fields(rscreen, resource, rtex->size,
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rtex->surface.bo_alignment);
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resource->flags |= RADEON_FLAG_HANDLE;
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if (!r600_alloc_resource(rscreen, resource)) {
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FREE(rtex);
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return NULL;
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@ -52,6 +52,7 @@ enum radeon_bo_flag { /* bitfield */
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RADEON_FLAG_GTT_WC = (1 << 0),
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RADEON_FLAG_CPU_ACCESS = (1 << 1),
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RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
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RADEON_FLAG_HANDLE = (1 << 3), /* the buffer most not be suballocated */
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};
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enum radeon_bo_usage { /* bitfield */
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@ -508,6 +508,9 @@ amdgpu_bo_create(struct radeon_winsys *rws,
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struct amdgpu_winsys_bo *bo;
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unsigned usage = 0, pb_cache_bucket;
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/* This flag is irrelevant for the cache. */
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flags &= ~RADEON_FLAG_HANDLE;
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/* Align size to page size. This is the minimum alignment for normal
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* BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
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* like constant/uniform buffers, can benefit from better and more reuse.
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@ -750,6 +750,9 @@ radeon_winsys_bo_create(struct radeon_winsys *rws,
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if (size > UINT_MAX)
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return NULL;
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/* This flag is irrelevant for the cache. */
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flags &= ~RADEON_FLAG_HANDLE;
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/* Align size to page size. This is the minimum alignment for normal
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* BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
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* like constant/uniform buffers, can benefit from better and more reuse.
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@ -620,7 +620,7 @@ radeon_cs_create_fence(struct radeon_winsys_cs *rcs)
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/* Create a fence, which is a dummy BO. */
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fence = cs->ws->base.buffer_create(&cs->ws->base, 1, 1,
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RADEON_DOMAIN_GTT, 0);
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RADEON_DOMAIN_GTT, RADEON_FLAG_HANDLE);
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/* Add the fence as a dummy relocation. */
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cs->ws->base.cs_add_buffer(rcs, fence,
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RADEON_USAGE_READWRITE, RADEON_DOMAIN_GTT,
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