anv: Leverage the shared L3$ config code
When Jordan first implement L3$ configuration for Vulkan, he copied+pasted from the GL driver because we had no good place to share it. Now that we have src/intel/common, we should be sharing these tables. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Jason Ekstrand
parent
49981891f7
commit
6448c0e324
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@ -52,7 +52,7 @@ typedef struct xcb_connection_t xcb_connection_t;
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typedef uint32_t xcb_visualid_t;
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typedef uint32_t xcb_window_t;
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struct anv_l3_config;
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struct gen_l3_config;
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#include <vulkan/vulkan.h>
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#include <vulkan/vulkan_intel.h>
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@ -1224,7 +1224,7 @@ struct anv_attachment_state {
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struct anv_cmd_state {
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/* PIPELINE_SELECT.PipelineSelection */
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uint32_t current_pipeline;
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const struct anv_l3_config * current_l3_config;
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const struct gen_l3_config * current_l3_config;
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uint32_t vb_dirty;
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anv_cmd_dirty_mask_t dirty;
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anv_cmd_dirty_mask_t compute_dirty;
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@ -1524,7 +1524,7 @@ struct anv_pipeline {
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uint32_t start[MESA_SHADER_GEOMETRY + 1];
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uint32_t size[MESA_SHADER_GEOMETRY + 1];
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uint32_t entries[MESA_SHADER_GEOMETRY + 1];
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const struct anv_l3_config * l3_config;
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const struct gen_l3_config * l3_config;
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uint32_t total_size;
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} urb;
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@ -23,285 +23,10 @@
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#include "anv_private.h"
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#include "common/gen_l3_config.h"
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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/**
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* Chunk of L3 cache reserved for some specific purpose.
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*/
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enum anv_l3_partition {
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/** Shared local memory. */
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L3P_SLM = 0,
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/** Unified return buffer. */
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L3P_URB,
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/** Union of DC and RO. */
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L3P_ALL,
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/** Data cluster RW partition. */
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L3P_DC,
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/** Union of IS, C and T. */
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L3P_RO,
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/** Instruction and state cache. */
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L3P_IS,
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/** Constant cache. */
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L3P_C,
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/** Texture cache. */
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L3P_T,
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/** Number of supported L3 partitions. */
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NUM_L3P
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};
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/**
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* L3 configuration represented as the number of ways allocated for each
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* partition. \sa get_l3_way_size().
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*/
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struct anv_l3_config {
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unsigned n[NUM_L3P];
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};
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#if GEN_GEN == 7
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/**
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* IVB/HSW validated L3 configurations. The first entry will be used as
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* default by gen7_restore_default_l3_config(), otherwise the ordering is
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* unimportant.
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*/
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static const struct anv_l3_config ivb_l3_configs[] = {
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/* SLM URB ALL DC RO IS C T */
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{{ 0, 32, 0, 0, 32, 0, 0, 0 }},
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{{ 0, 32, 0, 16, 16, 0, 0, 0 }},
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{{ 0, 32, 0, 4, 0, 8, 4, 16 }},
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{{ 0, 28, 0, 8, 0, 8, 4, 16 }},
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{{ 0, 28, 0, 16, 0, 8, 4, 8 }},
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{{ 0, 28, 0, 8, 0, 16, 4, 8 }},
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{{ 0, 28, 0, 0, 0, 16, 4, 16 }},
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{{ 0, 32, 0, 0, 0, 16, 0, 16 }},
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{{ 0, 28, 0, 4, 32, 0, 0, 0 }},
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{{ 16, 16, 0, 16, 16, 0, 0, 0 }},
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{{ 16, 16, 0, 8, 0, 8, 8, 8 }},
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{{ 16, 16, 0, 4, 0, 8, 4, 16 }},
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{{ 16, 16, 0, 4, 0, 16, 4, 8 }},
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{{ 16, 16, 0, 0, 32, 0, 0, 0 }},
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{{ 0 }}
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};
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#endif
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#if GEN_GEN == 7 && !GEN_IS_HASWELL
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/**
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* VLV validated L3 configurations. \sa ivb_l3_configs.
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*/
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static const struct anv_l3_config vlv_l3_configs[] = {
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/* SLM URB ALL DC RO IS C T */
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{{ 0, 64, 0, 0, 32, 0, 0, 0 }},
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{{ 0, 80, 0, 0, 16, 0, 0, 0 }},
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{{ 0, 80, 0, 8, 8, 0, 0, 0 }},
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{{ 0, 64, 0, 16, 16, 0, 0, 0 }},
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{{ 0, 60, 0, 4, 32, 0, 0, 0 }},
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{{ 32, 32, 0, 16, 16, 0, 0, 0 }},
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{{ 32, 40, 0, 8, 16, 0, 0, 0 }},
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{{ 32, 40, 0, 16, 8, 0, 0, 0 }},
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{{ 0 }}
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};
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#endif
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#if GEN_GEN == 8
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/**
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* BDW validated L3 configurations. \sa ivb_l3_configs.
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*/
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static const struct anv_l3_config bdw_l3_configs[] = {
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/* SLM URB ALL DC RO IS C T */
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{{ 0, 48, 48, 0, 0, 0, 0, 0 }},
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{{ 0, 48, 0, 16, 32, 0, 0, 0 }},
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{{ 0, 32, 0, 16, 48, 0, 0, 0 }},
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{{ 0, 32, 0, 0, 64, 0, 0, 0 }},
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{{ 0, 32, 64, 0, 0, 0, 0, 0 }},
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{{ 24, 16, 48, 0, 0, 0, 0, 0 }},
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{{ 24, 16, 0, 16, 32, 0, 0, 0 }},
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{{ 24, 16, 0, 32, 16, 0, 0, 0 }},
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{{ 0 }}
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};
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#endif
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#if GEN_GEN == 8 || GEN_GEN == 9
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/**
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* CHV/SKL validated L3 configurations. \sa ivb_l3_configs.
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*/
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static const struct anv_l3_config chv_l3_configs[] = {
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/* SLM URB ALL DC RO IS C T */
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{{ 0, 48, 48, 0, 0, 0, 0, 0 }},
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{{ 0, 48, 0, 16, 32, 0, 0, 0 }},
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{{ 0, 32, 0, 16, 48, 0, 0, 0 }},
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{{ 0, 32, 0, 0, 64, 0, 0, 0 }},
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{{ 0, 32, 64, 0, 0, 0, 0, 0 }},
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{{ 32, 16, 48, 0, 0, 0, 0, 0 }},
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{{ 32, 16, 0, 16, 32, 0, 0, 0 }},
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{{ 32, 16, 0, 32, 16, 0, 0, 0 }},
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{{ 0 }}
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};
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#endif
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/**
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* Return a zero-terminated array of validated L3 configurations for the
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* specified device.
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*/
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static inline const struct anv_l3_config *
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get_l3_configs(const struct gen_device_info *devinfo)
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{
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assert(devinfo->gen == GEN_GEN);
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#if GEN_IS_HASWELL
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return ivb_l3_configs;
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#elif GEN_GEN == 7
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return (devinfo->is_baytrail ? vlv_l3_configs : ivb_l3_configs);
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#elif GEN_GEN == 8
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return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
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#elif GEN_GEN == 9
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return chv_l3_configs;
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#else
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#error GEN not supported
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#endif
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}
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/**
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* Return the size of an L3 way in KB.
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*/
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static unsigned
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get_l3_way_size(const struct gen_device_info *devinfo)
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{
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if (devinfo->is_baytrail)
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return 2;
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else if (devinfo->is_cherryview || devinfo->gt == 1)
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return 4;
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else
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return 8 * devinfo->num_slices;
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}
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/**
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* L3 configuration represented as a vector of weights giving the desired
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* relative size of each partition. The scale is arbitrary, only the ratios
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* between weights will have an influence on the selection of the closest L3
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* configuration.
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*/
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struct anv_l3_weights {
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float w[NUM_L3P];
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};
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/**
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* L1-normalize a vector of L3 partition weights.
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*/
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static struct anv_l3_weights
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norm_l3_weights(struct anv_l3_weights w)
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{
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float sz = 0;
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for (unsigned i = 0; i < NUM_L3P; i++)
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sz += w.w[i];
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for (unsigned i = 0; i < NUM_L3P; i++)
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w.w[i] /= sz;
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return w;
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}
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/**
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* Get the relative partition weights of the specified L3 configuration.
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*/
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static struct anv_l3_weights
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get_config_l3_weights(const struct anv_l3_config *cfg)
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{
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if (cfg) {
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struct anv_l3_weights w;
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for (unsigned i = 0; i < NUM_L3P; i++)
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w.w[i] = cfg->n[i];
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return norm_l3_weights(w);
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} else {
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const struct anv_l3_weights w = { { 0 } };
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return w;
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}
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}
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/**
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* Distance between two L3 configurations represented as vectors of weights.
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* Usually just the L1 metric except when the two configurations are
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* considered incompatible in which case the distance will be infinite. Note
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* that the compatibility condition is asymmetric -- They will be considered
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* incompatible whenever the reference configuration \p w0 requires SLM, DC,
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* or URB but \p w1 doesn't provide it.
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*/
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static float
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diff_l3_weights(struct anv_l3_weights w0, struct anv_l3_weights w1)
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{
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if ((w0.w[L3P_SLM] && !w1.w[L3P_SLM]) ||
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(w0.w[L3P_DC] && !w1.w[L3P_DC] && !w1.w[L3P_ALL]) ||
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(w0.w[L3P_URB] && !w1.w[L3P_URB])) {
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return HUGE_VALF;
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} else {
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float dw = 0;
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for (unsigned i = 0; i < NUM_L3P; i++)
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dw += fabs(w0.w[i] - w1.w[i]);
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return dw;
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}
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}
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/**
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* Return the closest validated L3 configuration for the specified device and
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* weight vector.
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*/
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static const struct anv_l3_config *
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get_l3_config(const struct gen_device_info *devinfo, struct anv_l3_weights w0)
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{
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const struct anv_l3_config *const cfgs = get_l3_configs(devinfo);
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const struct anv_l3_config *cfg_best = NULL;
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float dw_best = HUGE_VALF;
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for (const struct anv_l3_config *cfg = cfgs; cfg->n[L3P_URB]; cfg++) {
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const float dw = diff_l3_weights(w0, get_config_l3_weights(cfg));
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if (dw < dw_best) {
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cfg_best = cfg;
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dw_best = dw;
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}
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}
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return cfg_best;
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}
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/**
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* Return a reasonable default L3 configuration for the specified device based
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* on whether SLM and DC are required. In the non-SLM non-DC case the result
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* is intended to approximately resemble the hardware defaults.
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*/
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static struct anv_l3_weights
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get_default_l3_weights(const struct gen_device_info *devinfo,
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bool needs_dc, bool needs_slm)
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{
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struct anv_l3_weights w = {{ 0 }};
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w.w[L3P_SLM] = needs_slm;
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w.w[L3P_URB] = 1.0;
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if (devinfo->gen >= 8) {
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w.w[L3P_ALL] = 1.0;
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} else {
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w.w[L3P_DC] = needs_dc ? 0.1 : 0;
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w.w[L3P_RO] = devinfo->is_baytrail ? 0.5 : 1.0;
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}
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return norm_l3_weights(w);
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}
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/**
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* Calculate the desired L3 partitioning based on the current state of the
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* pipeline. For now this simply returns the conservative defaults calculated
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@ -309,7 +34,7 @@ get_default_l3_weights(const struct gen_device_info *devinfo,
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* more statistics from the pipeline state (e.g. guess of expected URB usage
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* and bound surfaces), or by using feed-back from performance counters.
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*/
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static struct anv_l3_weights
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static struct gen_l3_weights
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get_pipeline_state_l3_weights(const struct anv_pipeline *pipeline)
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{
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bool needs_dc = false, needs_slm = false;
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@ -325,8 +50,8 @@ get_pipeline_state_l3_weights(const struct anv_pipeline *pipeline)
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needs_slm |= prog_data->total_shared;
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}
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return get_default_l3_weights(&pipeline->device->info,
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needs_dc, needs_slm);
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return gen_get_default_l3_weights(&pipeline->device->info,
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needs_dc, needs_slm);
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}
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#define emit_lri(batch, reg, imm) \
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@ -344,9 +69,9 @@ get_pipeline_state_l3_weights(const struct anv_pipeline *pipeline)
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*/
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static void
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setup_l3_config(struct anv_cmd_buffer *cmd_buffer/*, struct brw_context *brw*/,
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const struct anv_l3_config *cfg)
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const struct gen_l3_config *cfg)
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{
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const bool has_slm = cfg->n[L3P_SLM];
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const bool has_slm = cfg->n[GEN_L3P_SLM];
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/* According to the hardware docs, the L3 partitioning can only be changed
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* while the pipeline is completely drained and the caches are flushed,
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@ -391,27 +116,30 @@ setup_l3_config(struct anv_cmd_buffer *cmd_buffer/*, struct brw_context *brw*/,
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#if GEN_GEN >= 8
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assert(!cfg->n[L3P_IS] && !cfg->n[L3P_C] && !cfg->n[L3P_T]);
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assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
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uint32_t l3cr;
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anv_pack_struct(&l3cr, GENX(L3CNTLREG),
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.SLMEnable = has_slm,
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.URBAllocation = cfg->n[L3P_URB],
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.ROAllocation = cfg->n[L3P_RO],
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.DCAllocation = cfg->n[L3P_DC],
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.AllAllocation = cfg->n[L3P_ALL]);
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.URBAllocation = cfg->n[GEN_L3P_URB],
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.ROAllocation = cfg->n[GEN_L3P_RO],
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.DCAllocation = cfg->n[GEN_L3P_DC],
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.AllAllocation = cfg->n[GEN_L3P_ALL]);
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/* Set up the L3 partitioning. */
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emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG), l3cr);
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#else
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const bool has_dc = cfg->n[L3P_DC] || cfg->n[L3P_ALL];
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const bool has_is = cfg->n[L3P_IS] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
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const bool has_c = cfg->n[L3P_C] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
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const bool has_t = cfg->n[L3P_T] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
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const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL];
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const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] ||
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cfg->n[GEN_L3P_ALL];
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const bool has_c = cfg->n[GEN_L3P_C] || cfg->n[GEN_L3P_RO] ||
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cfg->n[GEN_L3P_ALL];
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const bool has_t = cfg->n[GEN_L3P_T] || cfg->n[GEN_L3P_RO] ||
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cfg->n[GEN_L3P_ALL];
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assert(!cfg->n[L3P_ALL]);
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assert(!cfg->n[GEN_L3P_ALL]);
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/* When enabled SLM only uses a portion of the L3 on half of the banks,
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* the matching space on the remaining banks has to be allocated to a
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@ -420,11 +148,11 @@ setup_l3_config(struct anv_cmd_buffer *cmd_buffer/*, struct brw_context *brw*/,
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*/
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const struct gen_device_info *devinfo = &cmd_buffer->device->info;
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const bool urb_low_bw = has_slm && !devinfo->is_baytrail;
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assert(!urb_low_bw || cfg->n[L3P_URB] == cfg->n[L3P_SLM]);
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assert(!urb_low_bw || cfg->n[GEN_L3P_URB] == cfg->n[GEN_L3P_SLM]);
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/* Minimum number of ways that can be allocated to the URB. */
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const unsigned n0_urb = (devinfo->is_baytrail ? 32 : 0);
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assert(cfg->n[L3P_URB] >= n0_urb);
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assert(cfg->n[GEN_L3P_URB] >= n0_urb);
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uint32_t l3sqcr1, l3cr2, l3cr3;
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anv_pack_struct(&l3sqcr1, GENX(L3SQCREG1),
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@ -440,19 +168,19 @@ setup_l3_config(struct anv_cmd_buffer *cmd_buffer/*, struct brw_context *brw*/,
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anv_pack_struct(&l3cr2, GENX(L3CNTLREG2),
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.SLMEnable = has_slm,
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.URBLowBandwidth = urb_low_bw,
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.URBAllocation = cfg->n[L3P_URB],
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.URBAllocation = cfg->n[GEN_L3P_URB],
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#if !GEN_IS_HASWELL
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.ALLAllocation = cfg->n[L3P_ALL],
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.ALLAllocation = cfg->n[GEN_L3P_ALL],
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#endif
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.ROAllocation = cfg->n[L3P_RO],
|
||||
.DCAllocation = cfg->n[L3P_DC]);
|
||||
.ROAllocation = cfg->n[GEN_L3P_RO],
|
||||
.DCAllocation = cfg->n[GEN_L3P_DC]);
|
||||
|
||||
anv_pack_struct(&l3cr3, GENX(L3CNTLREG3),
|
||||
.ISAllocation = cfg->n[L3P_IS],
|
||||
.ISAllocation = cfg->n[GEN_L3P_IS],
|
||||
.ISLowBandwidth = 0,
|
||||
.CAllocation = cfg->n[L3P_C],
|
||||
.CAllocation = cfg->n[GEN_L3P_C],
|
||||
.CLowBandwidth = 0,
|
||||
.TAllocation = cfg->n[L3P_T],
|
||||
.TAllocation = cfg->n[GEN_L3P_T],
|
||||
.TLowBandwidth = 0);
|
||||
|
||||
/* Set up the L3 partitioning. */
|
||||
|
|
@ -479,51 +207,15 @@ setup_l3_config(struct anv_cmd_buffer *cmd_buffer/*, struct brw_context *brw*/,
|
|||
|
||||
}
|
||||
|
||||
/**
|
||||
* Return the unit brw_context::urb::size is expressed in, in KB. \sa
|
||||
* gen_device_info::urb::size.
|
||||
*/
|
||||
static unsigned
|
||||
get_urb_size_scale(const struct gen_device_info *devinfo)
|
||||
{
|
||||
return (devinfo->gen >= 8 ? devinfo->num_slices : 1);
|
||||
}
|
||||
|
||||
void
|
||||
genX(setup_pipeline_l3_config)(struct anv_pipeline *pipeline)
|
||||
{
|
||||
const struct anv_l3_weights w = get_pipeline_state_l3_weights(pipeline);
|
||||
const struct gen_l3_weights w = get_pipeline_state_l3_weights(pipeline);
|
||||
const struct gen_device_info *devinfo = &pipeline->device->info;
|
||||
const struct anv_l3_config *const cfg = get_l3_config(devinfo, w);
|
||||
pipeline->urb.l3_config = cfg;
|
||||
|
||||
unsigned sz = cfg->n[L3P_URB] * get_l3_way_size(devinfo);
|
||||
|
||||
#if GEN_GEN == 9
|
||||
/* From the SKL "L3 Allocation and Programming" documentation:
|
||||
*
|
||||
* "URB is limited to 1008KB due to programming restrictions. This is not
|
||||
* a restriction of the L3 implementation, but of the FF and other clients.
|
||||
* Therefore, in a GT4 implementation it is possible for the programmed
|
||||
* allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
|
||||
* only 1008KB of this will be used."
|
||||
*/
|
||||
sz = MIN2(1008, sz);
|
||||
#endif
|
||||
|
||||
pipeline->urb.total_size = sz / get_urb_size_scale(devinfo);
|
||||
}
|
||||
|
||||
/**
|
||||
* Print out the specified L3 configuration.
|
||||
*/
|
||||
static void
|
||||
dump_l3_config(const struct anv_l3_config *cfg)
|
||||
{
|
||||
fprintf(stderr, "SLM=%d URB=%d ALL=%d DC=%d RO=%d IS=%d C=%d T=%d\n",
|
||||
cfg->n[L3P_SLM], cfg->n[L3P_URB], cfg->n[L3P_ALL],
|
||||
cfg->n[L3P_DC], cfg->n[L3P_RO],
|
||||
cfg->n[L3P_IS], cfg->n[L3P_C], cfg->n[L3P_T]);
|
||||
pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
|
||||
pipeline->urb.total_size =
|
||||
gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -531,7 +223,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
|
|||
const struct anv_pipeline *pipeline)
|
||||
{
|
||||
struct anv_cmd_state *state = &cmd_buffer->state;
|
||||
const struct anv_l3_config *const cfg = pipeline->urb.l3_config;
|
||||
const struct gen_l3_config *const cfg = pipeline->urb.l3_config;
|
||||
assert(cfg);
|
||||
if (cfg != state->current_l3_config) {
|
||||
setup_l3_config(cmd_buffer, cfg);
|
||||
|
|
@ -539,7 +231,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
|
|||
|
||||
if (unlikely(INTEL_DEBUG & DEBUG_L3)) {
|
||||
fprintf(stderr, "L3 config transition: ");
|
||||
dump_l3_config(cfg);
|
||||
gen_dump_l3_config(cfg, stderr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue