intel: Pull the guts of gen7_l3_state.c into a shared helper
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Jason Ekstrand
parent
979d0aca62
commit
49981891f7
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@ -8,7 +8,9 @@ BLORP_FILES = \
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COMMON_FILES = \
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common/gen_device_info.c \
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common/gen_device_info.h
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common/gen_device_info.h \
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common/gen_l3_config.c \
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common/gen_l3_config.h
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GENXML_GENERATED_FILES = \
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genxml/gen4_pack.h \
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@ -0,0 +1,304 @@
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/*
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* Copyright (c) 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <stdlib.h>
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#include <math.h>
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#include "util/macros.h"
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#include "main/macros.h"
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#include "gen_l3_config.h"
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/**
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* IVB/HSW validated L3 configurations. The first entry will be used as
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* default by gen7_restore_default_l3_config(), otherwise the ordering is
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* unimportant.
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*/
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static const struct gen_l3_config ivb_l3_configs[] = {
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/* SLM URB ALL DC RO IS C T */
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{{ 0, 32, 0, 0, 32, 0, 0, 0 }},
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{{ 0, 32, 0, 16, 16, 0, 0, 0 }},
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{{ 0, 32, 0, 4, 0, 8, 4, 16 }},
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{{ 0, 28, 0, 8, 0, 8, 4, 16 }},
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{{ 0, 28, 0, 16, 0, 8, 4, 8 }},
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{{ 0, 28, 0, 8, 0, 16, 4, 8 }},
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{{ 0, 28, 0, 0, 0, 16, 4, 16 }},
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{{ 0, 32, 0, 0, 0, 16, 0, 16 }},
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{{ 0, 28, 0, 4, 32, 0, 0, 0 }},
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{{ 16, 16, 0, 16, 16, 0, 0, 0 }},
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{{ 16, 16, 0, 8, 0, 8, 8, 8 }},
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{{ 16, 16, 0, 4, 0, 8, 4, 16 }},
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{{ 16, 16, 0, 4, 0, 16, 4, 8 }},
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{{ 16, 16, 0, 0, 32, 0, 0, 0 }},
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{{ 0 }}
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};
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/**
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* VLV validated L3 configurations. \sa ivb_l3_configs.
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*/
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static const struct gen_l3_config vlv_l3_configs[] = {
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/* SLM URB ALL DC RO IS C T */
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{{ 0, 64, 0, 0, 32, 0, 0, 0 }},
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{{ 0, 80, 0, 0, 16, 0, 0, 0 }},
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{{ 0, 80, 0, 8, 8, 0, 0, 0 }},
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{{ 0, 64, 0, 16, 16, 0, 0, 0 }},
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{{ 0, 60, 0, 4, 32, 0, 0, 0 }},
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{{ 32, 32, 0, 16, 16, 0, 0, 0 }},
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{{ 32, 40, 0, 8, 16, 0, 0, 0 }},
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{{ 32, 40, 0, 16, 8, 0, 0, 0 }},
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{{ 0 }}
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};
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/**
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* BDW validated L3 configurations. \sa ivb_l3_configs.
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*/
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static const struct gen_l3_config bdw_l3_configs[] = {
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/* SLM URB ALL DC RO IS C T */
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{{ 0, 48, 48, 0, 0, 0, 0, 0 }},
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{{ 0, 48, 0, 16, 32, 0, 0, 0 }},
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{{ 0, 32, 0, 16, 48, 0, 0, 0 }},
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{{ 0, 32, 0, 0, 64, 0, 0, 0 }},
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{{ 0, 32, 64, 0, 0, 0, 0, 0 }},
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{{ 24, 16, 48, 0, 0, 0, 0, 0 }},
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{{ 24, 16, 0, 16, 32, 0, 0, 0 }},
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{{ 24, 16, 0, 32, 16, 0, 0, 0 }},
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{{ 0 }}
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};
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/**
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* CHV/SKL validated L3 configurations. \sa ivb_l3_configs.
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*/
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static const struct gen_l3_config chv_l3_configs[] = {
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/* SLM URB ALL DC RO IS C T */
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{{ 0, 48, 48, 0, 0, 0, 0, 0 }},
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{{ 0, 48, 0, 16, 32, 0, 0, 0 }},
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{{ 0, 32, 0, 16, 48, 0, 0, 0 }},
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{{ 0, 32, 0, 0, 64, 0, 0, 0 }},
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{{ 0, 32, 64, 0, 0, 0, 0, 0 }},
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{{ 32, 16, 48, 0, 0, 0, 0, 0 }},
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{{ 32, 16, 0, 16, 32, 0, 0, 0 }},
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{{ 32, 16, 0, 32, 16, 0, 0, 0 }},
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{{ 0 }}
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};
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/**
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* Return a zero-terminated array of validated L3 configurations for the
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* specified device.
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*/
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static const struct gen_l3_config *
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get_l3_configs(const struct gen_device_info *devinfo)
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{
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switch (devinfo->gen) {
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case 7:
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return (devinfo->is_baytrail ? vlv_l3_configs : ivb_l3_configs);
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case 8:
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return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
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case 9:
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return chv_l3_configs;
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default:
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unreachable("Not implemented");
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}
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}
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/**
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* L1-normalize a vector of L3 partition weights.
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*/
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static struct gen_l3_weights
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norm_l3_weights(struct gen_l3_weights w)
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{
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float sz = 0;
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for (unsigned i = 0; i < GEN_NUM_L3P; i++)
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sz += w.w[i];
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for (unsigned i = 0; i < GEN_NUM_L3P; i++)
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w.w[i] /= sz;
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return w;
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}
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/**
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* Get the relative partition weights of the specified L3 configuration.
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*/
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struct gen_l3_weights
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gen_get_l3_config_weights(const struct gen_l3_config *cfg)
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{
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if (cfg) {
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struct gen_l3_weights w;
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for (unsigned i = 0; i < GEN_NUM_L3P; i++)
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w.w[i] = cfg->n[i];
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return norm_l3_weights(w);
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} else {
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const struct gen_l3_weights w = { { 0 } };
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return w;
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}
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}
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/**
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* Distance between two L3 configurations represented as vectors of weights.
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* Usually just the L1 metric except when the two configurations are
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* considered incompatible in which case the distance will be infinite. Note
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* that the compatibility condition is asymmetric -- They will be considered
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* incompatible whenever the reference configuration \p w0 requires SLM, DC,
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* or URB but \p w1 doesn't provide it.
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*/
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float
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gen_diff_l3_weights(struct gen_l3_weights w0, struct gen_l3_weights w1)
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{
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if ((w0.w[GEN_L3P_SLM] && !w1.w[GEN_L3P_SLM]) ||
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(w0.w[GEN_L3P_DC] && !w1.w[GEN_L3P_DC] && !w1.w[GEN_L3P_ALL]) ||
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(w0.w[GEN_L3P_URB] && !w1.w[GEN_L3P_URB])) {
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return HUGE_VALF;
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} else {
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float dw = 0;
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for (unsigned i = 0; i < GEN_NUM_L3P; i++)
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dw += fabs(w0.w[i] - w1.w[i]);
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return dw;
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}
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}
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/**
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* Return a reasonable default L3 configuration for the specified device based
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* on whether SLM and DC are required. In the non-SLM non-DC case the result
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* is intended to approximately resemble the hardware defaults.
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*/
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struct gen_l3_weights
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gen_get_default_l3_weights(const struct gen_device_info *devinfo,
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bool needs_dc, bool needs_slm)
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{
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struct gen_l3_weights w = {{ 0 }};
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w.w[GEN_L3P_SLM] = needs_slm;
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w.w[GEN_L3P_URB] = 1.0;
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if (devinfo->gen >= 8) {
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w.w[GEN_L3P_ALL] = 1.0;
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} else {
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w.w[GEN_L3P_DC] = needs_dc ? 0.1 : 0;
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w.w[GEN_L3P_RO] = devinfo->is_baytrail ? 0.5 : 1.0;
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}
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return norm_l3_weights(w);
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}
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/**
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* Get the default L3 configuration
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*/
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const struct gen_l3_config *
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gen_get_default_l3_config(const struct gen_device_info *devinfo)
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{
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/* For efficiency assume that the first entry of the array matches the
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* default configuration.
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*/
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const struct gen_l3_config *const cfg = get_l3_configs(devinfo);
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assert(cfg == gen_get_l3_config(devinfo,
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gen_get_default_l3_weights(devinfo, false, false)));
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return cfg;
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}
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/**
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* Return the closest validated L3 configuration for the specified device and
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* weight vector.
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*/
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const struct gen_l3_config *
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gen_get_l3_config(const struct gen_device_info *devinfo,
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struct gen_l3_weights w0)
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{
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const struct gen_l3_config *const cfgs = get_l3_configs(devinfo);
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const struct gen_l3_config *cfg_best = NULL;
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float dw_best = HUGE_VALF;
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for (const struct gen_l3_config *cfg = cfgs; cfg->n[GEN_L3P_URB]; cfg++) {
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const float dw = gen_diff_l3_weights(w0, gen_get_l3_config_weights(cfg));
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if (dw < dw_best) {
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cfg_best = cfg;
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dw_best = dw;
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}
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}
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return cfg_best;
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}
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/**
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* Return the size of an L3 way in KB.
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*/
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static unsigned
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get_l3_way_size(const struct gen_device_info *devinfo)
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{
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if (devinfo->is_baytrail)
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return 2;
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else if (devinfo->is_cherryview || devinfo->gt == 1)
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return 4;
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else
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return 8 * devinfo->num_slices;
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}
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/**
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* Return the unit brw_context::urb::size is expressed in, in KB. \sa
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* gen_device_info::urb::size.
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*/
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static unsigned
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get_urb_size_scale(const struct gen_device_info *devinfo)
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{
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return (devinfo->gen >= 8 ? devinfo->num_slices : 1);
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}
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unsigned
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gen_get_l3_config_urb_size(const struct gen_device_info *devinfo,
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const struct gen_l3_config *cfg)
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{
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/* From the SKL "L3 Allocation and Programming" documentation:
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*
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* "URB is limited to 1008KB due to programming restrictions. This is not
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* a restriction of the L3 implementation, but of the FF and other clients.
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* Therefore, in a GT4 implementation it is possible for the programmed
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* allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
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* only 1008KB of this will be used."
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*/
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const unsigned max = (devinfo->gen == 9 ? 1008 : ~0);
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return MIN2(max, cfg->n[GEN_L3P_URB] * get_l3_way_size(devinfo)) /
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get_urb_size_scale(devinfo);
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}
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/**
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* Print out the specified L3 configuration.
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*/
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void
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gen_dump_l3_config(const struct gen_l3_config *cfg, FILE *fp)
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{
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fprintf(stderr, "SLM=%d URB=%d ALL=%d DC=%d RO=%d IS=%d C=%d T=%d\n",
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cfg->n[GEN_L3P_SLM], cfg->n[GEN_L3P_URB], cfg->n[GEN_L3P_ALL],
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cfg->n[GEN_L3P_DC], cfg->n[GEN_L3P_RO],
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cfg->n[GEN_L3P_IS], cfg->n[GEN_L3P_C], cfg->n[GEN_L3P_T]);
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}
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@ -0,0 +1,90 @@
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/*
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* Copyright (c) 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <stdio.h>
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#include "gen_device_info.h"
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/**
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* Chunk of L3 cache reserved for some specific purpose.
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*/
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enum gen_l3_partition {
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/** Shared local memory. */
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GEN_L3P_SLM = 0,
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/** Unified return buffer. */
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GEN_L3P_URB,
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/** Union of DC and RO. */
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GEN_L3P_ALL,
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/** Data cluster RW partition. */
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GEN_L3P_DC,
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/** Union of IS, C and T. */
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GEN_L3P_RO,
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/** Instruction and state cache. */
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GEN_L3P_IS,
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/** Constant cache. */
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GEN_L3P_C,
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/** Texture cache. */
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GEN_L3P_T,
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/** Number of supported L3 partitions. */
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GEN_NUM_L3P
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};
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/**
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* L3 configuration represented as the number of ways allocated for each
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* partition. \sa get_l3_way_size().
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*/
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struct gen_l3_config {
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unsigned n[GEN_NUM_L3P];
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};
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/**
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* L3 configuration represented as a vector of weights giving the desired
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* relative size of each partition. The scale is arbitrary, only the ratios
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* between weights will have an influence on the selection of the closest L3
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* configuration.
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*/
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struct gen_l3_weights {
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float w[GEN_NUM_L3P];
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};
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float gen_diff_l3_weights(struct gen_l3_weights w0, struct gen_l3_weights w1);
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struct gen_l3_weights
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gen_get_default_l3_weights(const struct gen_device_info *devinfo,
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bool needs_dc, bool needs_slm);
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struct gen_l3_weights
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gen_get_l3_config_weights(const struct gen_l3_config *cfg);
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const struct gen_l3_config *
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gen_get_default_l3_config(const struct gen_device_info *devinfo);
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const struct gen_l3_config *
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gen_get_l3_config(const struct gen_device_info *devinfo,
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struct gen_l3_weights w0);
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unsigned
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gen_get_l3_config_urb_size(const struct gen_device_info *devinfo,
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const struct gen_l3_config *cfg);
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void gen_dump_l3_config(const struct gen_l3_config *cfg, FILE *fp);
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@ -734,7 +734,7 @@ enum brw_predicate_state {
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struct shader_times;
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struct brw_l3_config;
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struct gen_l3_config;
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/**
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* brw_context is derived from gl_context.
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@ -1317,7 +1317,7 @@ struct brw_context
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int baseinstance;
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struct {
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const struct brw_l3_config *config;
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const struct gen_l3_config *config;
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} l3;
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struct {
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@ -21,272 +21,13 @@
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* IN THE SOFTWARE.
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*/
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#include "common/gen_l3_config.h"
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#include "brw_context.h"
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#include "brw_defines.h"
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#include "brw_state.h"
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#include "intel_batchbuffer.h"
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/**
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* Chunk of L3 cache reserved for some specific purpose.
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*/
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enum brw_l3_partition {
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/** Shared local memory. */
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L3P_SLM = 0,
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/** Unified return buffer. */
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L3P_URB,
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/** Union of DC and RO. */
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L3P_ALL,
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/** Data cluster RW partition. */
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L3P_DC,
|
||||
/** Union of IS, C and T. */
|
||||
L3P_RO,
|
||||
/** Instruction and state cache. */
|
||||
L3P_IS,
|
||||
/** Constant cache. */
|
||||
L3P_C,
|
||||
/** Texture cache. */
|
||||
L3P_T,
|
||||
/** Number of supported L3 partitions. */
|
||||
NUM_L3P
|
||||
};
|
||||
|
||||
/**
|
||||
* L3 configuration represented as the number of ways allocated for each
|
||||
* partition. \sa get_l3_way_size().
|
||||
*/
|
||||
struct brw_l3_config {
|
||||
unsigned n[NUM_L3P];
|
||||
};
|
||||
|
||||
/**
|
||||
* IVB/HSW validated L3 configurations. The first entry will be used as
|
||||
* default by gen7_restore_default_l3_config(), otherwise the ordering is
|
||||
* unimportant.
|
||||
*/
|
||||
static const struct brw_l3_config ivb_l3_configs[] = {
|
||||
/* SLM URB ALL DC RO IS C T */
|
||||
{{ 0, 32, 0, 0, 32, 0, 0, 0 }},
|
||||
{{ 0, 32, 0, 16, 16, 0, 0, 0 }},
|
||||
{{ 0, 32, 0, 4, 0, 8, 4, 16 }},
|
||||
{{ 0, 28, 0, 8, 0, 8, 4, 16 }},
|
||||
{{ 0, 28, 0, 16, 0, 8, 4, 8 }},
|
||||
{{ 0, 28, 0, 8, 0, 16, 4, 8 }},
|
||||
{{ 0, 28, 0, 0, 0, 16, 4, 16 }},
|
||||
{{ 0, 32, 0, 0, 0, 16, 0, 16 }},
|
||||
{{ 0, 28, 0, 4, 32, 0, 0, 0 }},
|
||||
{{ 16, 16, 0, 16, 16, 0, 0, 0 }},
|
||||
{{ 16, 16, 0, 8, 0, 8, 8, 8 }},
|
||||
{{ 16, 16, 0, 4, 0, 8, 4, 16 }},
|
||||
{{ 16, 16, 0, 4, 0, 16, 4, 8 }},
|
||||
{{ 16, 16, 0, 0, 32, 0, 0, 0 }},
|
||||
{{ 0 }}
|
||||
};
|
||||
|
||||
/**
|
||||
* VLV validated L3 configurations. \sa ivb_l3_configs.
|
||||
*/
|
||||
static const struct brw_l3_config vlv_l3_configs[] = {
|
||||
/* SLM URB ALL DC RO IS C T */
|
||||
{{ 0, 64, 0, 0, 32, 0, 0, 0 }},
|
||||
{{ 0, 80, 0, 0, 16, 0, 0, 0 }},
|
||||
{{ 0, 80, 0, 8, 8, 0, 0, 0 }},
|
||||
{{ 0, 64, 0, 16, 16, 0, 0, 0 }},
|
||||
{{ 0, 60, 0, 4, 32, 0, 0, 0 }},
|
||||
{{ 32, 32, 0, 16, 16, 0, 0, 0 }},
|
||||
{{ 32, 40, 0, 8, 16, 0, 0, 0 }},
|
||||
{{ 32, 40, 0, 16, 8, 0, 0, 0 }},
|
||||
{{ 0 }}
|
||||
};
|
||||
|
||||
/**
|
||||
* BDW validated L3 configurations. \sa ivb_l3_configs.
|
||||
*/
|
||||
static const struct brw_l3_config bdw_l3_configs[] = {
|
||||
/* SLM URB ALL DC RO IS C T */
|
||||
{{ 0, 48, 48, 0, 0, 0, 0, 0 }},
|
||||
{{ 0, 48, 0, 16, 32, 0, 0, 0 }},
|
||||
{{ 0, 32, 0, 16, 48, 0, 0, 0 }},
|
||||
{{ 0, 32, 0, 0, 64, 0, 0, 0 }},
|
||||
{{ 0, 32, 64, 0, 0, 0, 0, 0 }},
|
||||
{{ 24, 16, 48, 0, 0, 0, 0, 0 }},
|
||||
{{ 24, 16, 0, 16, 32, 0, 0, 0 }},
|
||||
{{ 24, 16, 0, 32, 16, 0, 0, 0 }},
|
||||
{{ 0 }}
|
||||
};
|
||||
|
||||
/**
|
||||
* CHV/SKL validated L3 configurations. \sa ivb_l3_configs.
|
||||
*/
|
||||
static const struct brw_l3_config chv_l3_configs[] = {
|
||||
/* SLM URB ALL DC RO IS C T */
|
||||
{{ 0, 48, 48, 0, 0, 0, 0, 0 }},
|
||||
{{ 0, 48, 0, 16, 32, 0, 0, 0 }},
|
||||
{{ 0, 32, 0, 16, 48, 0, 0, 0 }},
|
||||
{{ 0, 32, 0, 0, 64, 0, 0, 0 }},
|
||||
{{ 0, 32, 64, 0, 0, 0, 0, 0 }},
|
||||
{{ 32, 16, 48, 0, 0, 0, 0, 0 }},
|
||||
{{ 32, 16, 0, 16, 32, 0, 0, 0 }},
|
||||
{{ 32, 16, 0, 32, 16, 0, 0, 0 }},
|
||||
{{ 0 }}
|
||||
};
|
||||
|
||||
/**
|
||||
* Return a zero-terminated array of validated L3 configurations for the
|
||||
* specified device.
|
||||
*/
|
||||
static const struct brw_l3_config *
|
||||
get_l3_configs(const struct gen_device_info *devinfo)
|
||||
{
|
||||
switch (devinfo->gen) {
|
||||
case 7:
|
||||
return (devinfo->is_baytrail ? vlv_l3_configs : ivb_l3_configs);
|
||||
|
||||
case 8:
|
||||
return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
|
||||
|
||||
case 9:
|
||||
return chv_l3_configs;
|
||||
|
||||
default:
|
||||
unreachable("Not implemented");
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Return the size of an L3 way in KB.
|
||||
*/
|
||||
static unsigned
|
||||
get_l3_way_size(const struct gen_device_info *devinfo)
|
||||
{
|
||||
if (devinfo->is_baytrail)
|
||||
return 2;
|
||||
|
||||
else if (devinfo->is_cherryview || devinfo->gt == 1)
|
||||
return 4;
|
||||
|
||||
else
|
||||
return 8 * devinfo->num_slices;
|
||||
}
|
||||
|
||||
/**
|
||||
* L3 configuration represented as a vector of weights giving the desired
|
||||
* relative size of each partition. The scale is arbitrary, only the ratios
|
||||
* between weights will have an influence on the selection of the closest L3
|
||||
* configuration.
|
||||
*/
|
||||
struct brw_l3_weights {
|
||||
float w[NUM_L3P];
|
||||
};
|
||||
|
||||
/**
|
||||
* L1-normalize a vector of L3 partition weights.
|
||||
*/
|
||||
static struct brw_l3_weights
|
||||
norm_l3_weights(struct brw_l3_weights w)
|
||||
{
|
||||
float sz = 0;
|
||||
|
||||
for (unsigned i = 0; i < NUM_L3P; i++)
|
||||
sz += w.w[i];
|
||||
|
||||
for (unsigned i = 0; i < NUM_L3P; i++)
|
||||
w.w[i] /= sz;
|
||||
|
||||
return w;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the relative partition weights of the specified L3 configuration.
|
||||
*/
|
||||
static struct brw_l3_weights
|
||||
get_config_l3_weights(const struct brw_l3_config *cfg)
|
||||
{
|
||||
if (cfg) {
|
||||
struct brw_l3_weights w;
|
||||
|
||||
for (unsigned i = 0; i < NUM_L3P; i++)
|
||||
w.w[i] = cfg->n[i];
|
||||
|
||||
return norm_l3_weights(w);
|
||||
} else {
|
||||
const struct brw_l3_weights w = { { 0 } };
|
||||
return w;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Distance between two L3 configurations represented as vectors of weights.
|
||||
* Usually just the L1 metric except when the two configurations are
|
||||
* considered incompatible in which case the distance will be infinite. Note
|
||||
* that the compatibility condition is asymmetric -- They will be considered
|
||||
* incompatible whenever the reference configuration \p w0 requires SLM, DC,
|
||||
* or URB but \p w1 doesn't provide it.
|
||||
*/
|
||||
static float
|
||||
diff_l3_weights(struct brw_l3_weights w0, struct brw_l3_weights w1)
|
||||
{
|
||||
if ((w0.w[L3P_SLM] && !w1.w[L3P_SLM]) ||
|
||||
(w0.w[L3P_DC] && !w1.w[L3P_DC] && !w1.w[L3P_ALL]) ||
|
||||
(w0.w[L3P_URB] && !w1.w[L3P_URB])) {
|
||||
return HUGE_VALF;
|
||||
|
||||
} else {
|
||||
float dw = 0;
|
||||
|
||||
for (unsigned i = 0; i < NUM_L3P; i++)
|
||||
dw += fabs(w0.w[i] - w1.w[i]);
|
||||
|
||||
return dw;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Return the closest validated L3 configuration for the specified device and
|
||||
* weight vector.
|
||||
*/
|
||||
static const struct brw_l3_config *
|
||||
get_l3_config(const struct gen_device_info *devinfo, struct brw_l3_weights w0)
|
||||
{
|
||||
const struct brw_l3_config *const cfgs = get_l3_configs(devinfo);
|
||||
const struct brw_l3_config *cfg_best = NULL;
|
||||
float dw_best = HUGE_VALF;
|
||||
|
||||
for (const struct brw_l3_config *cfg = cfgs; cfg->n[L3P_URB]; cfg++) {
|
||||
const float dw = diff_l3_weights(w0, get_config_l3_weights(cfg));
|
||||
|
||||
if (dw < dw_best) {
|
||||
cfg_best = cfg;
|
||||
dw_best = dw;
|
||||
}
|
||||
}
|
||||
|
||||
return cfg_best;
|
||||
}
|
||||
|
||||
/**
|
||||
* Return a reasonable default L3 configuration for the specified device based
|
||||
* on whether SLM and DC are required. In the non-SLM non-DC case the result
|
||||
* is intended to approximately resemble the hardware defaults.
|
||||
*/
|
||||
static struct brw_l3_weights
|
||||
get_default_l3_weights(const struct gen_device_info *devinfo,
|
||||
bool needs_dc, bool needs_slm)
|
||||
{
|
||||
struct brw_l3_weights w = {{ 0 }};
|
||||
|
||||
w.w[L3P_SLM] = needs_slm;
|
||||
w.w[L3P_URB] = 1.0;
|
||||
|
||||
if (devinfo->gen >= 8) {
|
||||
w.w[L3P_ALL] = 1.0;
|
||||
} else {
|
||||
w.w[L3P_DC] = needs_dc ? 0.1 : 0;
|
||||
w.w[L3P_RO] = devinfo->is_baytrail ? 0.5 : 1.0;
|
||||
}
|
||||
|
||||
return norm_l3_weights(w);
|
||||
}
|
||||
|
||||
/**
|
||||
* Calculate the desired L3 partitioning based on the current state of the
|
||||
* pipeline. For now this simply returns the conservative defaults calculated
|
||||
|
|
@ -294,7 +35,7 @@ get_default_l3_weights(const struct gen_device_info *devinfo,
|
|||
* more statistics from the pipeline state (e.g. guess of expected URB usage
|
||||
* and bound surfaces), or by using feed-back from performance counters.
|
||||
*/
|
||||
static struct brw_l3_weights
|
||||
static struct gen_l3_weights
|
||||
get_pipeline_state_l3_weights(const struct brw_context *brw)
|
||||
{
|
||||
const struct brw_stage_state *stage_states[] = {
|
||||
|
|
@ -317,21 +58,24 @@ get_pipeline_state_l3_weights(const struct brw_context *brw)
|
|||
needs_slm |= prog_data && prog_data->total_shared;
|
||||
}
|
||||
|
||||
return get_default_l3_weights(brw->intelScreen->devinfo,
|
||||
needs_dc, needs_slm);
|
||||
return gen_get_default_l3_weights(brw->intelScreen->devinfo,
|
||||
needs_dc, needs_slm);
|
||||
}
|
||||
|
||||
/**
|
||||
* Program the hardware to use the specified L3 configuration.
|
||||
*/
|
||||
static void
|
||||
setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg)
|
||||
setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
|
||||
{
|
||||
const bool has_dc = cfg->n[L3P_DC] || cfg->n[L3P_ALL];
|
||||
const bool has_is = cfg->n[L3P_IS] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
|
||||
const bool has_c = cfg->n[L3P_C] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
|
||||
const bool has_t = cfg->n[L3P_T] || cfg->n[L3P_RO] || cfg->n[L3P_ALL];
|
||||
const bool has_slm = cfg->n[L3P_SLM];
|
||||
const bool has_dc = cfg->n[GEN_L3P_DC] || cfg->n[GEN_L3P_ALL];
|
||||
const bool has_is = cfg->n[GEN_L3P_IS] || cfg->n[GEN_L3P_RO] ||
|
||||
cfg->n[GEN_L3P_ALL];
|
||||
const bool has_c = cfg->n[GEN_L3P_C] || cfg->n[GEN_L3P_RO] ||
|
||||
cfg->n[GEN_L3P_ALL];
|
||||
const bool has_t = cfg->n[GEN_L3P_T] || cfg->n[GEN_L3P_RO] ||
|
||||
cfg->n[GEN_L3P_ALL];
|
||||
const bool has_slm = cfg->n[GEN_L3P_SLM];
|
||||
|
||||
/* According to the hardware docs, the L3 partitioning can only be changed
|
||||
* while the pipeline is completely drained and the caches are flushed,
|
||||
|
|
@ -372,7 +116,7 @@ setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg)
|
|||
PIPE_CONTROL_CS_STALL);
|
||||
|
||||
if (brw->gen >= 8) {
|
||||
assert(!cfg->n[L3P_IS] && !cfg->n[L3P_C] && !cfg->n[L3P_T]);
|
||||
assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
|
||||
|
||||
BEGIN_BATCH(3);
|
||||
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
|
||||
|
|
@ -380,15 +124,15 @@ setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg)
|
|||
/* Set up the L3 partitioning. */
|
||||
OUT_BATCH(GEN8_L3CNTLREG);
|
||||
OUT_BATCH((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
|
||||
SET_FIELD(cfg->n[L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
|
||||
SET_FIELD(cfg->n[L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
|
||||
SET_FIELD(cfg->n[L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
|
||||
SET_FIELD(cfg->n[L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
|
||||
SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
|
||||
SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
|
||||
SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
|
||||
SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
|
||||
|
||||
ADVANCE_BATCH();
|
||||
|
||||
} else {
|
||||
assert(!cfg->n[L3P_ALL]);
|
||||
assert(!cfg->n[GEN_L3P_ALL]);
|
||||
|
||||
/* When enabled SLM only uses a portion of the L3 on half of the banks,
|
||||
* the matching space on the remaining banks has to be allocated to a
|
||||
|
|
@ -396,11 +140,11 @@ setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg)
|
|||
* lower-bandwidth 2-bank address hashing mode.
|
||||
*/
|
||||
const bool urb_low_bw = has_slm && !brw->is_baytrail;
|
||||
assert(!urb_low_bw || cfg->n[L3P_URB] == cfg->n[L3P_SLM]);
|
||||
assert(!urb_low_bw || cfg->n[GEN_L3P_URB] == cfg->n[GEN_L3P_SLM]);
|
||||
|
||||
/* Minimum number of ways that can be allocated to the URB. */
|
||||
const unsigned n0_urb = (brw->is_baytrail ? 32 : 0);
|
||||
assert(cfg->n[L3P_URB] >= n0_urb);
|
||||
assert(cfg->n[GEN_L3P_URB] >= n0_urb);
|
||||
|
||||
BEGIN_BATCH(7);
|
||||
OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2));
|
||||
|
|
@ -418,15 +162,15 @@ setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg)
|
|||
/* Set up the L3 partitioning. */
|
||||
OUT_BATCH(GEN7_L3CNTLREG2);
|
||||
OUT_BATCH((has_slm ? GEN7_L3CNTLREG2_SLM_ENABLE : 0) |
|
||||
SET_FIELD(cfg->n[L3P_URB] - n0_urb, GEN7_L3CNTLREG2_URB_ALLOC) |
|
||||
SET_FIELD(cfg->n[GEN_L3P_URB] - n0_urb, GEN7_L3CNTLREG2_URB_ALLOC) |
|
||||
(urb_low_bw ? GEN7_L3CNTLREG2_URB_LOW_BW : 0) |
|
||||
SET_FIELD(cfg->n[L3P_ALL], GEN7_L3CNTLREG2_ALL_ALLOC) |
|
||||
SET_FIELD(cfg->n[L3P_RO], GEN7_L3CNTLREG2_RO_ALLOC) |
|
||||
SET_FIELD(cfg->n[L3P_DC], GEN7_L3CNTLREG2_DC_ALLOC));
|
||||
SET_FIELD(cfg->n[GEN_L3P_ALL], GEN7_L3CNTLREG2_ALL_ALLOC) |
|
||||
SET_FIELD(cfg->n[GEN_L3P_RO], GEN7_L3CNTLREG2_RO_ALLOC) |
|
||||
SET_FIELD(cfg->n[GEN_L3P_DC], GEN7_L3CNTLREG2_DC_ALLOC));
|
||||
OUT_BATCH(GEN7_L3CNTLREG3);
|
||||
OUT_BATCH(SET_FIELD(cfg->n[L3P_IS], GEN7_L3CNTLREG3_IS_ALLOC) |
|
||||
SET_FIELD(cfg->n[L3P_C], GEN7_L3CNTLREG3_C_ALLOC) |
|
||||
SET_FIELD(cfg->n[L3P_T], GEN7_L3CNTLREG3_T_ALLOC));
|
||||
OUT_BATCH(SET_FIELD(cfg->n[GEN_L3P_IS], GEN7_L3CNTLREG3_IS_ALLOC) |
|
||||
SET_FIELD(cfg->n[GEN_L3P_C], GEN7_L3CNTLREG3_C_ALLOC) |
|
||||
SET_FIELD(cfg->n[GEN_L3P_T], GEN7_L3CNTLREG3_T_ALLOC));
|
||||
|
||||
ADVANCE_BATCH();
|
||||
|
||||
|
|
@ -446,36 +190,15 @@ setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg)
|
|||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Return the unit brw_context::urb::size is expressed in, in KB. \sa
|
||||
* gen_device_info::urb::size.
|
||||
*/
|
||||
static unsigned
|
||||
get_urb_size_scale(const struct gen_device_info *devinfo)
|
||||
{
|
||||
return (devinfo->gen >= 8 ? devinfo->num_slices : 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* Update the URB size in the context state for the specified L3
|
||||
* configuration.
|
||||
*/
|
||||
static void
|
||||
update_urb_size(struct brw_context *brw, const struct brw_l3_config *cfg)
|
||||
update_urb_size(struct brw_context *brw, const struct gen_l3_config *cfg)
|
||||
{
|
||||
const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
|
||||
/* From the SKL "L3 Allocation and Programming" documentation:
|
||||
*
|
||||
* "URB is limited to 1008KB due to programming restrictions. This is not
|
||||
* a restriction of the L3 implementation, but of the FF and other clients.
|
||||
* Therefore, in a GT4 implementation it is possible for the programmed
|
||||
* allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
|
||||
* only 1008KB of this will be used."
|
||||
*/
|
||||
const unsigned max = (devinfo->gen == 9 ? 1008 : ~0);
|
||||
const unsigned sz =
|
||||
MIN2(max, cfg->n[L3P_URB] * get_l3_way_size(devinfo)) /
|
||||
get_urb_size_scale(devinfo);
|
||||
const unsigned sz = gen_get_l3_config_urb_size(devinfo, cfg);
|
||||
|
||||
if (brw->urb.size != sz) {
|
||||
brw->urb.size = sz;
|
||||
|
|
@ -483,23 +206,11 @@ update_urb_size(struct brw_context *brw, const struct brw_l3_config *cfg)
|
|||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Print out the specified L3 configuration.
|
||||
*/
|
||||
static void
|
||||
dump_l3_config(const struct brw_l3_config *cfg)
|
||||
{
|
||||
fprintf(stderr, "SLM=%d URB=%d ALL=%d DC=%d RO=%d IS=%d C=%d T=%d\n",
|
||||
cfg->n[L3P_SLM], cfg->n[L3P_URB], cfg->n[L3P_ALL],
|
||||
cfg->n[L3P_DC], cfg->n[L3P_RO],
|
||||
cfg->n[L3P_IS], cfg->n[L3P_C], cfg->n[L3P_T]);
|
||||
}
|
||||
|
||||
static void
|
||||
emit_l3_state(struct brw_context *brw)
|
||||
{
|
||||
const struct brw_l3_weights w = get_pipeline_state_l3_weights(brw);
|
||||
const float dw = diff_l3_weights(w, get_config_l3_weights(brw->l3.config));
|
||||
const struct gen_l3_weights w = get_pipeline_state_l3_weights(brw);
|
||||
const float dw = gen_diff_l3_weights(w, gen_get_l3_config_weights(brw->l3.config));
|
||||
/* The distance between any two compatible weight vectors cannot exceed two
|
||||
* due to the triangle inequality.
|
||||
*/
|
||||
|
|
@ -518,8 +229,8 @@ emit_l3_state(struct brw_context *brw)
|
|||
small_dw_threshold : large_dw_threshold);
|
||||
|
||||
if (dw > dw_threshold && brw->can_do_pipelined_register_writes) {
|
||||
const struct brw_l3_config *const cfg =
|
||||
get_l3_config(brw->intelScreen->devinfo, w);
|
||||
const struct gen_l3_config *const cfg =
|
||||
gen_get_l3_config(brw->intelScreen->devinfo, w);
|
||||
|
||||
setup_l3_config(brw, cfg);
|
||||
update_urb_size(brw, cfg);
|
||||
|
|
@ -527,7 +238,7 @@ emit_l3_state(struct brw_context *brw)
|
|||
|
||||
if (unlikely(INTEL_DEBUG & DEBUG_L3)) {
|
||||
fprintf(stderr, "L3 config transition (%f > %f): ", dw, dw_threshold);
|
||||
dump_l3_config(cfg);
|
||||
gen_dump_l3_config(cfg, stderr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -582,12 +293,7 @@ void
|
|||
gen7_restore_default_l3_config(struct brw_context *brw)
|
||||
{
|
||||
const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
|
||||
/* For efficiency assume that the first entry of the array matches the
|
||||
* default configuration.
|
||||
*/
|
||||
const struct brw_l3_config *const cfg = get_l3_configs(devinfo);
|
||||
assert(cfg == get_l3_config(devinfo,
|
||||
get_default_l3_weights(devinfo, false, false)));
|
||||
const struct gen_l3_config *const cfg = gen_get_default_l3_config(devinfo);
|
||||
|
||||
if (cfg != brw->l3.config && brw->can_do_pipelined_register_writes) {
|
||||
setup_l3_config(brw, cfg);
|
||||
|
|
|
|||
Loading…
Reference in New Issue